adau1361 Analog Devices, Inc., adau1361 Datasheet - Page 42

• Manufacturer Part Number: adau1361
• Description: Stereo, Low Power, 96 Khz, 24-bit Audio Codec With Integrated Pll
• Manufacturer: Analog Devices, Inc.

ADAU1361
APPLICATIONS INFORMATION
POWER SUPPLY BYPASS CAPACITORS
Each analog and digital power supply pin should be bypassed to
its nearest appropriate ground pin with a sin
T
a
v
from the power and ground pins or, when equidistant placement
is not possible, slightly closer to the power pin. Thermal connec-
tions to the ground planes should be made on the far side of the
capacitor.
Each supply signal
single bulk capacito
GSM NOISE FILTER
In mobile phone applications, excessive 217 Hz GSM noise on
the analog supply pins can degrade the audio quality. To avoid
this problem, it is recommended that an L-C filter be us
series with the bypass capacitors for the AVDD pi
sh
series between AV
s possible, and the trace should stay on a single layer with no
ias. For maximum effectiveness, locate the capacitor equidistant
he connections to each side of the capacitor should be as short
ould consis
Figure 60. Recommended Power Supply Bypass Capacitor Layout
Figure 61. GSM Filter on the Analog Supply Pins
t of a 1.2 nH inductor and a 9.1 pF
DD and ground, as shown i
on the board should also
r (10 μF to 47 μF).
AVDD
CAPACITOR
TO VDD
AVDD
1.2nH
VDD
0.1µF
0.1µF
10µF
+
TO GND
9.1pF
GND
gle 100 nF capacitor.
be bypassed with a
n Figure 61.
capacitor in
ns. This filter
ed in
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GROUNDING
A single ground plane should be used in the application la out.
Components in an analog sig
from digital signals.
EXPOSED PAD PCB DESIGN
The ADAU1361 has an exposed pad on the underside of the
LFCSP. This pad is used to couple the package to the PCB for
heat dissipation when using the outputs to drive earpiece or
headphone loads. When designing a board for the ADAU1361,
special consideration should be given to the following:
•
•
A copper layer equal in size to the exposed pad should be
on all layers of the board, from top to bottom, and should
connect somewhere to a dedicated copper board layer (see
Figure 62).
V
allowing for efficient heat and energy conductivity. For an
example, see Figure 63, which has nine vias arranged in a
3 inch × 3 inch grid in the pad area.
ias should be placed to connect all layers of copper,
Figure 62. Exposed Pad Layout Example, Side View
Figure 63. Exposed Pad Layout Example, Top View
VIAS
nal path should be placed away
COPPER SQUARES
TOP
GROUND
POWER
BOTTOM
y