adau1361 Analog Devices, Inc., adau1361 Datasheet - Page 52

• Manufacturer Part Number: adau1361
• Description: Stereo, Low Power, 96 Khz, 24-bit Audio Codec With Integrated Pll
• Manufacturer: Analog Devices, Inc.

ADAU1361
R11: ALC Control 0 16401 (0x4011)
Bit 7
Table 38. ALC Control 0 Register
Bit
[7:6]
[5:3]
[2:0]
PGASLEW[1:0
Bit Name
PGASLEW[1:0]
ALCMAX[2:0]
ALCSEL[2:0]
Bit 6
]
Description
PGA volume slew time when the ALC is off. The slew time is the period of time that a volume increase or decrease
takes to ramp
and Register R9 (right differential input volume control).
Setting
00
01
10
11
The max
protects
Setting
000
001
010
011
100
101
110
111
ALC select. These bits set the channels that are controlled by the ALC. When set to right only, the ALC responds
only to the right channel input and controls the gain of the right PGA amplifier only. When set to left only, the
ALC responds only to the left chan
stereo, the ALC responds to the greater of the left or right channel a
right PGA amplifiers. The PGA must be off if manual control of the vo
Setting
000
001
010
011
100
101
110
111
Bit 5
imum ALC gain sets a li
small signals from exce
up or ramp down to the target volume set in Register R8 (left differential input volume control)
Bit 4
AL
CM
mit to
Slew Time
24 ms (default)
48 ms
96 ms
Off
Maximum
−12 dB (default)
−6 dB
0 dB
6 dB
12 dB
18 dB
24 dB
30 dB
Channels
Off (default)
Right only
Left only
Stereo
Reserved
R
Reserved
Reserved
ssive amp
AX[2:0]
Rev. 0 | Page 52 of 80
eserved
nel input and controls the gain of the left PGA amplifier only. When set to
the amount of gain that the ALC can provide to the input signal. This
lification.
ALC Gain
Bit 3
Bit 2
nd controls the gain of both the left and
lume is desired.
Bit 1
ALCSEL[2:0
]
Bit 0