lan9303m Standard Microsystems Corp., lan9303m Datasheet - Page 187
lan9303m
Manufacturer Part Number
lan9303m
Description
Small Form Factor Three Port 10/100 Managed Ethernet Switch With Dual Mii/rmii/turbo Mii
Manufacturer
Standard Microsystems Corp.
Datasheet
1.LAN9303M.pdf
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Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
SMSC LAN9303M/LAN9303Mi
BITS
4:0
5
10BASE-T Half Duplex
This bit determines the advertised 10BASE-T half duplex capability.
0: 10BASE-T half duplex ability not advertised
1: 10BASE-T half duplex ability advertised
Selector Field
This field identifies the type of message being sent by Auto-Negotiation.
00001: IEEE 802.3
Note 13.30 The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on
Note 13.31 The Virtual PHY does not support next page capability. This bit value will always be 0.
Note 13.32 The
Note 13.33 The
Note 13.34 Virtual 100BASE-T4 is not supported.
Note 13.35 The Virtual PHY supports only IEEE 802.3. Only a value of 00001b should be used in this
a DWORD boundary. When accessed serially (through the MII management protocol), the
register is 16-bits wide.
strap is low (both Symmetric and Asymmetric are advertised), and 0 if the
manual_FC_strap_0
Configuration strap values are latched upon the de-assertion of a chip-level reset as
described in
field.
Symmetric Pause
Remote Fault
Section 4.2.4, "Configuration Straps," on page
DESCRIPTION
bit is not useful since there is no actual link partner to send a fault to.
strap is high (neither Symmetric and Asymmetric are advertised).
and
DATASHEET
Asymmetric Pause
187
bits default to 1 if the
51.
TYPE
R/W
R/W
Revision 1.3 (08-27-09)
manual_FC_strap_0
Note 13.35
DEFAULT
00001b
1b
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