lan9303m Standard Microsystems Corp., lan9303m Datasheet - Page 213

• Manufacturer Part Number: lan9303m
• Description: Small Form Factor Three Port 10/100 Managed Ethernet Switch With Dual Mii/rmii/turbo Mii
• Manufacturer: Standard Microsystems Corp.

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
SMSC LAN9303M/LAN9303Mi
autoneg_strap_x
BITS
4:0
0
0
0
0
1
1
1
1
Selector Field
This field identifies the type of message being sent by Auto-Negotiation.
00001: IEEE 802.3
Note 13.67 The Asymmetric Pause and Symmetric Pause bits are loaded into the PHY registers by
Note 13.68 For Port 1 operating in an external mode (MII PHY, RMII PHY, or MII MAC mode), the
Note 13.69 For Port 1 operating in an external mode (MII PHY, RMII PHY, or MII MAC mode), the
Note 13.70 For Port 1 operating in an external mode (MII PHY, RMII PHY, or MII MAC mode), the
Table 13.9 10BASE-T Full Duplex Advertisement Default Value
speed_strap_x
the EEPROM Loader. For Port 1 operating in an external mode (MII PHY, RMII PHY, or
MII MAC mode), the default value of both these bits is 0 and is independent of any strap.
For Port 1 operating in Internal PHY mode and for all operating modes of Port 2, the
default values of the Asymmetric Pause and Symmetric Pause bits are determined by the
M a n u a l F l ow C o n t r o l E n a b l e St r a p (
manual_FC_strap_2
the Symmetric Pause bit defaults to 1 and the Asymmetric Pause bit defaults to the setting
of the Full Duplex Flow Control Enable Strap
FD_FC_strap_2
bits default to 0. Configuration strap values are latched upon the de-assertion of a chip-
level reset as described in
Section 4.2.4, "Configuration Straps," on page 51
default value of this bit is 0. For Port 1 operating in Internal PHY mode and for all operating
modes of Port 2, the default value is 1.
default value of this bit is 1 and is independent of any strap. For Port 1 operating in Internal
PHY mode and for all operating modes of Port 2, the default value of this bit is determined
by the logical OR of the Auto-Negotiation Enable strap
autoneg_strap_2
(speed_strap_1
Strap
the default behavior of this bit. Configuration strap values are latched upon the de-
assertion of a chip-level reset as described in
page
definitions.
default value of this bit is 1 and is independent of any strap. For Port 1 operating in Internal
PHY mode and for all operating modes of Port 2, the default value of this bit is determined
by the logical OR of the Auto-Negotiation Enable strap
autoneg_strap_2
51. Refer to
(duplex_strap_1
0
0
1
1
0
0
1
1
DESCRIPTION
for Port 2 PHY). When the Manual Flow Control Enable Strap is 1, both
for Port 1 PHY,
for Port 2 PHY) with the logical AND of the negated Speed Select strap
for Port 2 PHY) and the negated Speed Select strap
Section 4.2.4, "Configuration Straps," on page 51
duplex_strap_x
for Port 2 PHY). When the Manual Flow Control Enable Strap is 0,
for Port 1 PHY,
DATASHEET
0
1
0
1
0
1
0
1
Section 4.2.4, "Configuration Straps," on page
213
speed_strap_2
duplex_strap_2
m an u a l _ F C _ s t r a p _1
Default 10BASE-T Full Duplex Value
Section 4.2.4, "Configuration Straps," on
for Port 2 PHY) and the Duplex Select
for configuration strap definitions.
(FD_FC_strap_1
for Port 2 PHY).
(autoneg_strap_1
(autoneg_strap_1
0
1
0
0
1
1
1
1
TYPE
R/W
for configuration strap
Revision 1.3 (08-27-09)
f o r P o r t 1 P H Y,
(speed_strap_1
Table 13.9
for Port 1 PHY,
for Port 1 PHY,
for Port 1 PHY,
DEFAULT
51. Refer to
00001b
defines
for