lan9303m Standard Microsystems Corp., lan9303m Datasheet - Page 191

• Manufacturer Part Number: lan9303m
• Description: Small Form Factor Three Port 10/100 Managed Ethernet Switch With Dual Mii/rmii/turbo Mii
• Manufacturer: Standard Microsystems Corp.

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
Datasheet
SMSC LAN9303M/LAN9303Mi
13.2.6.7
31:16
BITS
15:5
4
3
2
1
0
RESERVED
(See
RESERVED
Parallel Detection Fault
This bit indicates whether a Parallel Detection Fault has been detected. This
bit is always 0.
0: A fault hasn’t been detected via the Parallel Detection function
1: A fault has been detected via the Parallel Detection function
Link Partner Next Page Able
This bit indicates whether the link partner has next page ability. This bit is
always 0.
0: Link partner does not contain next page capability
1: Link partner contains next page capability
Local Device Next Page Able
This bit indicates whether the local device has next page ability. This bit is
always 0.
0: Local device does not contain next page capability
1: Local device contains next page capability
Page Received
This bit indicates the reception of a new page.
0: A new page has not been received
1: A new page has been received
Link Partner Auto-Negotiation Able
This bit indicates the Auto-negotiation ability of the link partner.
0: Link partner is not Auto-Negotiation able
1: Link partner is Auto-Negotiation able
Virtual PHY Auto-Negotiation Expansion Register (VPHY_AN_EXP)
This register is used in the Auto-Negotiation process.
Note 13.40 The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on
Note 13.41 Since the Virtual PHY link partner is emulated, there is never a Parallel Detection Fault
Note 13.42 Next page ability is not supported by the Virtual PHY or emulated link partner.
Note 13.43 The
Note 13.44 The emulated link partner will show Auto-Negotiation able unless Auto-Negotiation fails (no
Note
13.40)
Offset:
Index (decimal):
a DWORD boundary. When accessed serially (through the MII management protocol), the
register is 16-bits wide.
and this bit is always 0.
thereafter when the Auto-Negotiation process is run.
common bits between the advertised ability and the link partner ability).
Page Received
1D8h
6
DESCRIPTION
bit is clear when read. It is first cleared on reset, but set shortly
DATASHEET
191
Size:
32 bits
RO/LH
TYPE
RO
RO
RO
RO
RO
RO
Revision 1.3 (08-27-09)
Note 13.41
Note 13.42
Note 13.42
Note 13.43
Note 13.44
DEFAULT
0b
0b
0b
1b
1b
-
-