peb20534h-52 Infineon Technologies Corporation, peb20534h-52 Datasheet - Page 111

• Manufacturer Part Number: peb20534h-52
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

Bus Arbitration Slave Initialization
The slave must start using internal resources only after reset. During reset, the default
is the slave mode. This is also done by setting bit LCONF.ABM=’0’. This enables the
slave mode of the bus arbitration signals. After this, the ’HLDEN’ bit in register LCONF
must be set.
Note: After setting the slave’s HLDEN bit, the LBREQ output of the slave might be
Note: The effect of resetting bit ’HLDEN’ in slave mode (whether the slave is in hold or
Operation of the Master/Slave Bus Arbitration:
The figure below shows the sequence of the bus arbitration signals in a master/slave
system. The start-up condition is that the master is in normal mode and operating on the
external bus, while the slave is in hold mode, operating from internal memory; the slave’s
bus interface is tristated. The marked time points in the diagram are explained in detail
in the following.
1) The slave detects that it has to perform an external bus access. It activates LBREQ to
low, which issues a hold request from the master.
2) The master activates LHLDA after releasing the bus. This initiates the slave’s exit from
hold sequence.
3a) When the master detects that it also has to perform external bus accesses, it
activates LBREQ to low. The earliest time for the master to activate LBREQ is one LBI
clock after the activation of the master’s LHLDA signal. However, the slave will ignore
this signal until it has completely taken over control of the external bus. In this way, it is
assured that the slave will at least perform one complete external bus access.
3b) If the master can operate from internal memory while it is in hold mode, it leaves the
LBREQ signal high until it detects that an external bus access has to be performed. The
slave therefore can stay on the bus as long as the master does not request the bus
again.
4) When the master has requested the bus again through activation of its LBREQ signal,
the slave will complete the current access and go into hold mode again. After completely
tristateing its bus interface, the slave deactivates its LBREQ signal, thus releasing the
master out of hold mode.
5) The master has terminated its hold mode and deactivates its LHLDA signal again.
Now the master again controls the external bus again.
Data Sheet
activated to low for a period of 2 LBI clock periods. If the master does not
recognize this hold request (it depends on the master’s transition detection time-
slot, whether this short pulse is detected), this pulse has no effect. If the master
recognizes this pulse, it might go into hold mode for one cycle. The exact timing in
this case will be defined later.
in normal mode) will be defined later. It is recommended to not reset the slave’s
’HLDEN’ bit after initialization.
111
Multi Function Port (MFP)
PEB 20534
PEF 20534
2000-05-30