peb20534h-52 Infineon Technologies Corporation, peb20534h-52 Datasheet - Page 266

• Manufacturer Part Number: peb20534h-52
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

Table 60
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Data Sheet
Bit 31
Bit 15
CHiFRDA
30
14
CHiFRDA:
Channel i First (Current) Receive Descriptor Address Register
(i=3...0)
i = 3...0
The DMA controller writes the first/current address of the channel
specific receive descriptor chain to these registers, i.e. the address of the
receive descriptor, the DMA receive channel i is currently working on.
These registers are only valid, if the DMA controller is operating in Last
Descriptor Address Mode (bit CMODE set to ’1’ in register GMODE).
29
13
28
12
read/write
0000 0000
Channel 0
0098
written by DSCC4
evaluated by CPU
27
11
H
26
10
H
CHiFRDA(15:2)
009C
Channel 1
25
9
CHiFRDA(31:16)
H
24
266
8
23
7
Channel 2
00A0
22
6
H
Detailed Register Description
21
5
20
4
Channel 3
00A4
19
(RX Channel 3...0)
3
H
18
2
PEB 20534
PEF 20534
2000-05-30
17
1
0
16
0
0