peb20534h-52 Infineon Technologies Corporation, peb20534h-52 Datasheet - Page 210
![no-image](/images/no-image-200.jpg)
peb20534h-52
Manufacturer Part Number
peb20534h-52
Description
Dma Supported Serial Communication Controller With 4 Channels
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEB20534H-52.pdf
(439 pages)
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The sequence of functional steps shown in table 32 are repeated as long as data
transmission is required and no error does occur.
The procedures to stop data transmission and/or reception are shown in table 33 and
table 34.
Table 33
Step
1
2
3
4
5
Table 34
Step
1
2
Data Sheet
Action by Host
HOLD bit ctrld.
Initialize CHiCFG register
- Interrupt Mask:
- DMAC Command (RDT)
Set GCMDR.AR.
Reset transmitter in SCC.
Action by Host
Disable
CCR2.RAC.
(RFI, TFI, RERR, TERR)
Stop Data Transmission
Stop Data Reception
receiver
LTDx/FTDx ctrld.
in
SCC
210
via
Action by DSCC4
The DMAC transmit channel discards
the transmit data stored internally and
returns to its reset state. No additional
data are read from the shared
memory.
Data stored internally in SCC are
discarded and transmission stops.
Action by DSCC4
SCC
received data stored internally are
transferred to the shared memory.
Reset and Initialization Procedure
stops
data
reception.
PEB 20534
PEF 20534
2000-05-30
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