peb20534h-52 Infineon Technologies Corporation, peb20534h-52 Datasheet - Page 59

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peb20534h-52

Manufacturer Part Number
peb20534h-52
Description
Dma Supported Serial Communication Controller With 4 Channels
Manufacturer
Infineon Technologies Corporation
Datasheet

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5.1
5.1.1
The following table provides an overview of all DMA Controller related registers. For
detailed register description refer to
A summary is provided in the following table:
Table 10
Data Sheet
Offset Address
relative to Base Address 0
(BAR0) in PCI Configuration
Space
(not DMA channel specific registers)
Global Control Registers
0000
0004
0008
Global Interrupt Queue Control Registers
000C
0010
003C
0040
Global Central FIFO Control Registers
H
H
H
H
H
H
H
DMAC Operational Description
DMAC Register Overview
DMA Controller Register Set
Register
GCMDR
GSTAR
GMODE
IQLENR0
IQLENR1
IQCFGBAR
IQPBAR
Chapter
59
10.
Meaning
Global Command Register
(see
Global Status Register
(see
Global Mode Register
(see
Interrupt Queue Length Register 0
(transmit/receive interrupt queues)
(see
Interrupt Queue Length Register 1
(configuration and peripheral interrupt
queue)
(see
Interrupt Queue Configuration Base
Address
(see
Interrupt Queue Peripheral Base
Address
(see
DMA Controller and Central FIFOs
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PEB 20534
PEF 20534
2000-05-30

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