peb20534h-52 Infineon Technologies Corporation, peb20534h-52 Datasheet - Page 353

• Manufacturer Part Number: peb20534h-52
• Description: Dma Supported Serial Communication Controller With 4 Channels
• Manufacturer: Infineon Technologies Corporation

Data Sheet
HDEN
BTYP(1:0)
RDEN
LBI HOLD Enable
This bit selects whether the LBI bus arbitration interface (pins LHOLD,
LHDLA, LBREQ) is enabled or disabled:
HDEN=’0’
HDEN=’1’
LBI Bus Type
The Local Bus Interface (LBI) supports 4 different bus configurations
which are selected via this bit field:
BTYP = ’00’ 8 bit address/data de-multiplexed bus
BTYP = ’01’ 8 bit address/data multiplexed bus
BTYP = ’10’ 16 bit address/data de-multiplexed bus
BTYP = ’11’ 16 bit address/data multiplexed bus
Note: The Peripheral Configuration must be selected accordingly (bit
LBI LRDY Enable
This bit selects whether the LRDY control input signal is evaluated or
ignored by the LBI:
RDEN=’0’
RDEN=’1’
field ’PERCFG’ in register GMODE).
The LBI bus arbitration interface is disabled. The DSCC4
(LBI) is always active bus master.
The LBI bus arbitration interface is enabled. The DSCC4
(LBI) shares bus mastership with one or more other bus
masters.
The DSCC4 can be default arbitration master or
arbitration slave depending on the setting of bit ’ABM’.
Input signal LRDY is ignored (but should be connected to
a defined level). The bus cycle depends only on the
selected number of wait states (bit field ’MCTC’).
Input signal LRDY is evaluated after the number of
selected wait states have been inserted. The bus
transaction is terminated after the first detection of
LRDY=’0’ (active).
353
Detailed Register Description
PEB 20534
PEF 20534
2000-05-30
(-)
(-)
(-)