uja1066 NXP Semiconductors, uja1066 Datasheet - Page 13

• Manufacturer Part Number: uja1066
• Description: High-speed Can Fail-safe System Basis Chip
• Manufacturer: NXP Semiconductors

NXP Semiconductors
UJA1066_2
Product data sheet
6.4.1 Watchdog start-up behavior
6.4.2 Watchdog window behavior
The following corrupted watchdog accesses result in an immediate system reset:
Any microcontroller-driven mode change is synchronized with a watchdog access by
reading the mode information and the watchdog period information from the same
register. This facilitates easy software flow control with defined watchdog behavior when
switching between different software modules.
Following any reset event, the watchdog is used to monitor the ECU start-up procedure. It
checks the behavior of the RSTN pin for clamping conditions or an interrupted reset wire.
If the watchdog is not properly served within t
monitoring procedure is restarted. If the watchdog is again not properly served, the
system enters Fail-safe mode (see also
When the SBC enters Normal mode, the Window mode of the watchdog is activated. This
ensures that the microcontroller operates within the required speed window; an operation
that is too fast or too slow will be detected. Watchdog triggering using Window mode is
illustrated in
The SBC provides 10 different period timings, scalable with a 4-factor watchdog prescaler.
The period can be changed within any valid trigger window. Whenever the watchdog is
triggered within the window time frame, the timer will be reset to start a new period.
Fig 4.
•
•
Illegal watchdog period coding; only ten different codes are valid
Illegal operating mode coding; only six different codes are valid
trigger
via SPI
Watchdog triggering using Window mode
Figure
trigger point
last
4.
trigger
restarts
period
Rev. 02 — 5 May 2009
too early
(with different duration if
trigger restarts period
earliest possible
trigger point
period
50 %
Figure
High-speed CAN fail-safe system basis chip
desired)
trigger
via SPI
trigger window
WD(init)
3, Start-up mode and Restart mode).
, another reset is forced and the
too early
latest possible
trigger point
100 %
new period
possible
earliest
trigger
50 %
point
window
trigger
possible
trigger
latest
100 %
point
UJA1066
© NXP B.V. 2009. All rights reserved.
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