uja1066 NXP Semiconductors, uja1066 Datasheet - Page 25

• Manufacturer Part Number: uja1066
• Description: High-speed Can Fail-safe System Basis Chip
• Manufacturer: NXP Semiconductors

NXP Semiconductors
UJA1066_2
Product data sheet
Fig 12. SPI timing protocol
SDO
SCS
SCK
SDI
6.12 SPI interface
floating
X
The Serial Peripheral Interface (SPI) provides the communication link with the
microcontroller, supporting multi-slave and multi-master operation. The SPI is configured
for full duplex data transfer, so status information is returned when new control data is
shifted in. The interface also offers a read-only access option, allowing registers to be
read back by the application without changing the register content.
The SPI uses four interface signals for synchronization and data transfer:
Bit sampling is performed on the falling clock edge and data is shifted on the rising clock
edge; see
X
•
•
•
•
sampled
SCS - SPI chip select; active LOW
SCK - SPI clock; default level is LOW due to low-power concept
SDI - SPI data input
SDO - SPI data output; floating when pin SCS is HIGH
01
MSB
MSB
Figure
02
12.
14
14
Rev. 02 — 5 May 2009
03
13
13
04
12
12
High-speed CAN fail-safe system basis chip
15
01
01
16
LSB
LSB
UJA1066
© NXP B.V. 2009. All rights reserved.
floating
mce634
X
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