uja1066 NXP Semiconductors, uja1066 Datasheet - Page 30

• Manufacturer Part Number: uja1066
• Description: High-speed Can Fail-safe System Basis Chip
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 7.
[1]
UJA1066_2
Product data sheet
Bit
11 to 8
7
6
5
4
3
2
0
1
The RSS bits are updated with each reset event and not cleared. The last reset event is captured.
System Status register bit description
Symbol
RSS[3:0]
CWS
-
EWS
WLS
TWS
SDMS
ENS
PWONS
6.12.5 System Diagnosis register
This register allows diagnostic information to be read back from the SBC. This register can
be read in all modes.
Description
Reset Source
CAN Wake-up Status
reserved
Edge Wake-up Status
WAKE Level Status
Temperature Warning
Status
Software Development
Mode Status
Enable Status
Power-on reset Status
[1]
Rev. 02 — 5 May 2009
…continued
Value
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
Function
power-on reset; first connection of BAT42 or BAT42 below
power-on voltage threshold or RSTN was forced LOW
externally
cyclic wake-up out of Sleep mode
low V1 supply; V1 has dropped below the selected reset
threshold
V1 current above threshold within Standby mode while
watchdog OFF behavior and reset option (V1CMC bit) are
selected
V3 voltage is down due to overload occurring during Sleep
mode
SBC successfully left Flash mode
SBC ready to enter Flash mode
CAN wake-up event
reserved for SBCs with LIN transceiver
local wake-up event (via pin WAKE)
wake-up out of Fail-safe mode
watchdog overflow
watchdog not initialized in time; t
watchdog triggered too early; window missed
illegal SPI access
interrupt not served within t
CAN wake-up detected; cleared upon read
no CAN wake-up
reserved for SBCs with LIN transceiver
pin WAKE negative edge detected; cleared upon read
pin WAKE no edge detected
pin WAKE above threshold
pin WAKE below threshold
chip temperature exceeds the warning limit
chip temperature is below the warning limit
Software Development mode on
Software Development mode off
pin EN output activated (V1-related HIGH level)
pin EN output released (LOW level)
power-on reset; cleared after a successfully entered
Normal mode
no power-on reset
High-speed CAN fail-safe system basis chip
RSTN(INT)
WD(init)
UJA1066
exceeded
© NXP B.V. 2009. All rights reserved.
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