uja1066 NXP Semiconductors, uja1066 Datasheet - Page 29

• Manufacturer Part Number: uja1066
• Description: High-speed Can Fail-safe System Basis Chip
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 6.
[1]
[2]
[3]
Table 7.
UJA1066_2
Product data sheet
Bit
11 to 6
Bit
15 and 14
13
12
The nominal watchdog periods are directly related to the SBC internal oscillator. The given values are valid for f
See
The watchdog is immediately disabled on entering Sleep mode, with watchdog OFF behavior selected, because pin RSTN is
immediately pulled LOW by the mode change. V1 is switched off after pulling pin RSTN LOW to guarantee a safe Sleep mode entry
without dips on V1. See
Section
Mode register bit description (bits 11 to 6)
System Status register bit description
Symbol
NWP[5:0]
Symbol
A1, A0
RRS
RO
6.12.4 System Status register
6.4.4.
This register allows status information to be read back from the SBC. This register can be
read in all modes.
Section
Description
Nominal
Watchdog Period
WDPRE = 11 (as
set in the Special
Mode register)
Description
register address
Read Register Select
Read Only
6.4.4.
Value
00 1001
00 1100
01 0010
01 0100
01 1011
10 0100
10 1101
11 0011
11 0101
11 0110
Rev. 02 — 5 May 2009
Value
00
0
1
0
[1]
…continued
Time
Normal
mode (ms)
14
28
56
112
140
168
196
224
252
280
Function
read System Status register
read System Status register without writing to Mode
register
read System Status register and write to Mode register
High-speed CAN fail-safe system basis chip
Standby
mode (ms)
70
140
280
560
1120
2240
3584
7168
14336
OFF
[2]
Flash mode
(ms)
70
140
280
560
1120
2240
3584
7168
14336
28672
osc
UJA1066
© NXP B.V. 2009. All rights reserved.
= 512 kHz.
Sleep mode
(ms)
560
1120
2240
3584
7168
10752
14336
21504
28672
OFF
[3]
29 of 69