ptn3700 NXP Semiconductors, ptn3700 Datasheet - Page 15

• Manufacturer Part Number: ptn3700
• Description: 1.8 V Simple Mobile Interface Link Bridge Ic
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PTN3700_1
Product data sheet
7.4.3.1 Pixel synchronization
7.4.3.2 PLL
7.4.3 PLL, PCLK, CLK and pixel synchronization
7.4.4 HS, VS and DE signal usage in various PTN3700 modes
PSS mode:
synchronization. At the receiver side, a PLL is needed to re-generate the bit clock,
translating to a higher receiver power dissipation.
FSS mode:
synchronization words are transmitted in the non-active display area for pixel
synchronization. The receiver PLL is powered down during this mode, hence the lower
power consumption when compared with PSS mode. The special embedded
synchronization words are guaranteed by design to never trigger false synchronization.
The PLL locks onto the PCLK input during transmit mode or the CLK input during receiver
mode. It generates an internal high-speed clock, which is phase-aligned to the input clock.
The PLL logic uses the lane select and transmit/receive status to determine the necessary
PLL bandwidth settings and PLL divider values automatically. The PLL is able to track
spread spectrum clocking to reduce EMI. The spread spectrum clock modulation
frequency can be from 30 kHz to 33 kHz.
Transmitter:
Receiver:
When frame mixing is not used in PSS mode, VS, HS, DE, R[7:0], G[7:0], B[7:0] are
treated as arbitrary user data. In this mode, PTN3700 functions as a pure serializer and
deserializer, and is unaware of the meaning or polarity of VS, HS, DE, R[7:0], G[7:0],
B[7:0]. In FSS mode, PTN3700 makes use of VS, HS and DE to implement pixel
synchronization with embedded sync words in the non-active display area.
When frame mixing is used, VS, HS, DE and R[7:0], G[7:0], B[7:0] are used to implement
NXP-patented frame mixing algorithm.
Table 8
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•
•
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PSS mode: Refer to
FSS mode: The output clock CLK is Double Data Rate (DDR) and both clock edges
are aligned to the data output.
PSS mode: The PLL generates an internal clock at serial bit frequency and locks to
the input clock CLK.
FSS mode: The receiver uses Double Data Rate (DDR) input clock CLK, which is
aligned to the data already.
summarizes the requirements of VS, HS, DE and RGB in various modes.
The serial clock CLK is truly synchronous with the serial data. Embedded
The serial clock CLK provides the word boundaries explicitly for frame
The internally generated clock is always aligned to the input clock PCLK.
Rev. 01 — 14 August 2007
Section
7.4.1.
1.8 V simple mobile interface link bridge IC
PTN3700
© NXP B.V. 2007. All rights reserved.
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