ptn3700 NXP Semiconductors, ptn3700 Datasheet - Page 8

• Manufacturer Part Number: ptn3700
• Description: 1.8 V Simple Mobile Interface Link Bridge Ic
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 4.
[1]
PTN3700_1
Product data sheet
Symbol
Parallel data outputs
R[7:0], G[7:0], B[7:0]
HS
VS
DE
A0, A1
High-speed serial inputs
D0+, D0 , D1+,
D1 , D2+, D2
CLK+, CLK
Clock outputs
PCLK
Configuration inputs
TX/RX
LS0, LS1
PSEL0, PSEL1
XSD
F/XS
FM
FSS
Parity output
CPO
Power supply
VDD
VDDA
GNDA
GND
Depends on configuration.
Pin description - Receiver mode
Pin
[1]
Type
CMOS
CMOS
CMOS
CMOS
CMOS
SubLVDS
receiver
SubLVDS
receiver
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Description
8-bit wide R, G, B pixel data outputs
Horizontal synchronization data output, active LOW
Vertical synchronization data output, active LOW
Data Enable output, active HIGH
Auxiliary output bits
Serialized high-speed differential subLVDS data inputs
Serialized high-speed differential subLVDS clock inputs
Pixel clock output
Transmitter/Receiver configuration input pin. When LOW, PTN3700 is configured
as receiver.
Serialization mode program pins. Select between 1, 2 or 3 lanes. See
Pin mirroring select pins. See
Shutdown mode input pin, active LOW, puts PTN3700 in lowest-power mode by
deactivating all circuitry. When HIGH, PTN3700 is either in Active mode or
awaiting clock input (Standby mode).
Program pin for fast (F/XS = HIGH) or slow (F/XS = LOW) parallel output and
PCLK slew rate
Frame Mixing select pin. When LOW, Frame Mixing is disabled and PTN3700
passes 24-bit video data transparently. When HIGH, Frame Mixing is enabled
and PTN3700 applies processing to the 24-bit video data resulting in 18-bit
output data words encoded with 24-bit color depth. Frame Mixing is only
available in Receiver mode.
Fully Source Synchronous select pin. When LOW, PTN3700 uses pseudo source
synchronous serial reception mode with the pixel clock as both the reference
frequency and the frame boundary delineation. When HIGH, PTN3700 uses true
source synchronous reception with embedded synchronization word decoding,
with the bit clock as reference frequency. On both Receiver and Transmitter, the
settings of the FSS pin should match. Otherwise the link will not function.
Parity error output, active HIGH. A HIGH level indicates a parity error was
detected in the current pixel data
power supply voltage
analog (PLL) power supply voltage
analog (PLL) ground
ground
Rev. 01 — 14 August 2007
Table 6
1.8 V simple mobile interface link bridge IC
and
Table
7.
PTN3700
© NXP B.V. 2007. All rights reserved.
Table
8 of 41
5.