w83977atg Winbond Electronics Corp America, w83977atg Datasheet - Page 55

• Manufacturer Part Number: w83977atg
• Description: W83877tf Plus Kbc, Gp I/o, Wake-up, Fir, Cir, Pb-free
• Manufacturer: Winbond Electronics Corp America

6.2.6
This register reflects the UART interrupt status, which is encoded by different interrupt sources into 3
bits.
Bit 7, 6: These two bits are set to a logical 1 when UFR bit 0 = 1.
Bit 5, 4: These two bits are always logic 0.
Bit 3: In 16450 mode, this bit is 0. In 16550 mode, both bit 3 and 2 are set to a logical 1 when a time-
Bit 2, 1: These two bits identify the priority level of the pending interrupt, as shown in the table below.
Bit 0: This bit is a logical 1 if there is no interrupt pending. If one of the interrupt sources has occurred,
TABLE 6-4 INTERRUPT CONTROL FUNCTION
** Bit 3 of ISR is enabled when bit 0 of UFR is logical 1.
Bit 3
0
0
0
1
0
0
out interrupt is pending.
this bit will be set to a logical 0.
Bit 2
Interrupt Status Register (ISR) (Read only)
0
1
1
1
0
0
ISR
Bit 1
0
1
0
0
1
0
Bit 0
1
0
0
0
0
0
7
Interrupt
priority
First
Second
Second
Third
Fourth
6
-
5
0
4
Interrupt Type
UART Receive
Status
RBR Data
Ready
FIFO Data
Timeout
TBR Empty
Handshake
status
0
3
-
INTERRUPT SET AND FUNCTION
2
- 47 -
1
Interrupt Source
1. OER = 1
3. NSER = 1 4. SBD = 1
1. RBR data ready
2. FIFO interrupt active level
Data present in RX FIFO for
4 characters period of time
since last access of RX
FIFO.
TBR empty
1. TCTS = 1
3. FERI = 1
No Interrupt pending
W83977ATF/W83977ATG
reached
0
0 if interrupt pending
Interrupt Status bit 0
Interrupt Status bit 1
Interrupt Status bit 2
FIFOs enabled
FIFOs enabled
2. PBER =1
4. TDCD = 1
2. TDSR = 1
Publication Release Date: May 2006
Clear Interrupt
Read USR
1. Read RBR
2. Read RBR until
FIFO data under
active level
Read RBR
1. Write data into
TBR
2. Read ISR (if
priority is third)
Read HSR
-
Revision 0.6