w83977atg Winbond Electronics Corp America, w83977atg Datasheet - Page 77

• Manufacturer Part Number: w83977atg
• Description: W83877tf Plus Kbc, Gp I/o, Wake-up, Fir, Cir, Pb-free
• Manufacturer: Winbond Electronics Corp America

7.6.5
These are combined to be a 13-bit register and up counter. The length of receiver frame will be
limited to the programmed frame length. If the received frame length is larger than the programmed
receiver frame length, the bit of MX_LEX (Maximum Length Exceed) will be set to 1. Simultaneously,
the receiver will not receive any more data to RX FIFO until the next start flag of the next frame, which
is defined in the physical layer IrDA 1.1. Reading these registers returns the number of received data
bytes of a frame from the receiver.
7.7
7.7.1
If flow control is enforced when UART switches mode from MIR/FIR to SIR, then the pre-programmed
baud rate of FCBLL/FCBHL are loaded into advanced baud rate divisor latch (ADBLL/ADBHL).
7.7.2
These registers control flow control mode operation as shown in the following table.
FC_MD
REG.
Reset
Value
Reset Value
Reset Value
ADDRESS
OFFSET
RFRLL
RFRLH
REG.
Set 5 - Flow control and IR control and Frame Status FIFO registers
Set4.Reg6, 7 - Receiver Frame Length (RFRLL/RFRLH)
Set5.Reg0, 1 - Flow Control Baud Rate Divisor Latch Register (FCDLL/ FCDHL)
Set5.Reg2 - Flow Control Mode Operation (FC_MD)
0
1
2
3
4
5
6
7
FC_MD2
BIT 7
0
BIT 7
bit 7
REGISTER
0
-
-
RFRLFH
RFRLFL
IRCFG1
FC_MD1
FCBHL
FC_MD
FCBLL
FS_FO
NAME
SSR
BIT 6
0
BIT 6
bit 6
0
-
-
FC_MD0
Flow Control Baud Rate Divisor Latch Register (Low Byte)
Flow Control Baud Rate Divisor Latch Register (High Byte)
Flow Control Mode Operation
Sets Select Register
Infrared Configure Register
Frame Status FIFO Register
Receiver Frame Length FIFO Low Byte
Receiver Frame Length FIFO High Byte
BIT 5
0
BIT 5
bit 5
0
-
-
BIT 4
- 69 -
0
-
BIT 4
bit 12
bit 4
W83977ATF/W83977ATG
0
0
REGISTER DESCRIPTION
FC_DSW
BIT 3
0
BIT 3
bit 11
bit 3
0
0
Publication Release Date: May 2006
EN_FD
BIT 2
0
BIT 2
bit 10
bit 2
0
0
EN_BRFC
BIT 1
0
BIT 1
bit 1
bit 9
0
0
Revision 0.6
EN_FC
BIT 0
BIT 0
0
bit 0
bit 8
0
0