w83977atg Winbond Electronics Corp America, w83977atg Datasheet - Page 79

• Manufacturer Part Number: w83977atg
• Description: W83877tf Plus Kbc, Gp I/o, Wake-up, Fir, Cir, Pb-free
• Manufacturer: Winbond Electronics Corp America

7.7.5
This register shows the bottom byte of frame status FIFO.
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
Bit 5:
Bit 4:
Bit 3~2:
Bit 1:
Bit 0:
Reset Value
FS_FO
REG.
Set5.Reg5 - Frame Status FIFO Register (FS_FO)
FSFDR - Frame Status FIFO Data Ready
Indicates that a data byte is valid in frame status FIFO bottom.
LST_FR - Lost Frame
Set to 1 when one or more frames have been lost.
Reserved.
MX_LEX - Maximum Frame Length Exceed
Set to 1 when incoming data exceeds programmed maximum frame length defined in Set4.Reg6 and
Set4.Reg7. This bit is in frame status FIFO bottom and is valid only when FSFDR=1 (Frame Status
FIFO Data Ready).
PHY_ERR - Physical Error
When receiving data, any physical layer error as defined in IrDA 1.1 will set this bit to 1. This bit is in
frame status FIFO bottom and is valid only when FSFDR=1 (Frame Status FIFO Data Ready).
CRC_ERR - CRC Error
Set to 1 when a bad CRC is received in a frame. This CRC belongs to physical layer as defined in
IrDA 1.1. This bit is in frame status FIFO bottom and is valid only when FSFDR=1 (Frame Status FIFO
Data Ready).
RX_OV - Received Data Overrun
Set to 1 when receiver FIFO overruns.
FSF_OV - Frame Status FIFO Overrun
Set to 1 When frame status FIFO overruns.
FEND_MD - Frame End Mode
A write to 1 enables hardware to split data stream into equal length frame automatically as defined
in Set4.Reg4 and Set4.Reg5, i.e., TFRLL/TFRLH.
AUX_RX - Auxiliary Receiver Pin
A write to 1 selects IRRX input pin. (Refer to Set7.Reg7.Bit5)
Reserved, write 0.
IRHSSL - Infrared Handshake Status Select
When set to 0, the HSR (Handshake Status Register) operates the same as defined in IR mode. A
write to 1 will disable HSR, and reading HSR returns 30H.
IR_FULL - Infrared Full Duplex Operation
When set to 0, IR module operates in half duplex. A write to 1 makes IR module operate in full
duplex.
FSFDR
BIT 7
0
LST_FR
BIT 6
0
BIT 5
0
-
MX_LEX
BIT 4
- 71 -
0
W83977ATF/W83977ATG
PHY_ERR CRC_ERR
BIT 3
0
Publication Release Date: May 2006
BIT 2
0
RX_OV
BIT 1
0
Revision 0.6
FSF_OV
BIT 0
0