hd64338023s Renesas Electronics Corporation., hd64338023s Datasheet - Page 110
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hd64338023s
Manufacturer Part Number
hd64338023s
Description
Renesas 8-bit Single-chip Microcomputer Super Low Power Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.HD64338023S.pdf
(697 pages)
- Current page: 110 of 697
- Download datasheet (6Mb)
Section 2 CPU
2.9.2
The BSET, BCLR, BNOT, BST, and BIST instructions read one byte of data, modify the data,
then write the data byte again. Special care is required when using these instructions in cases
where two registers are assigned to the same address, in the case of registers that include write-
only bits, and when the instruction accesses an I/O port.
Order of Operation
1
2
3
1. Bit manipulation in two registers assigned to the same address
Example 1: timer load register and timer counter
Figure 2.18 shows an example in which two timer registers share the same address. When a bit
manipulation instruction accesses the timer load register and timer counter of a reloadable timer,
since these two registers share the same address, the following operations take place.
Order of Operation
1
2
3
The timer counter is counting, so the value read is not necessarily the same as the value in the
timer load register. As a result, bits other than the intended bit in the timer load register may be
modified to the timer counter value.
Rev. 7.00 Mar 10, 2005 page 68 of 652
REJ09B0042-0700
Read
Modify
Write
Read
Modify
Write
Notes on Bit Manipulation
Count clock
Operation
Read byte data at the designated address
Modify a designated bit in the read data
Write the altered byte data to the designated address
Operation
Timer counter data is read (one byte)
The CPU modifies (sets or resets) the bit designated in the instruction
The altered byte data is written to the timer load register
Figure 2.18 Timer Configuration Example
Timer load register
Timer counter
Reload
Read
Write
Internal
data bus
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