hd64338023s Renesas Electronics Corporation., hd64338023s Datasheet - Page 97

• Manufacturer Part Number: hd64338023s
• Description: Renesas 8-bit Single-chip Microcomputer Super Low Power Series
• Manufacturer: Renesas Electronics Corporation.

2.6
CPU operation is synchronized by a system clock (φ) or a subclock (φ
clock signals see section 4, Clock Pulse Generators. The period from a rising edge of φ or φ
the next rising edge is called one state. A bus cycle consists of two states or three states. The
cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules.
2.6.1
Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing
access in byte or word size. Figure 2.11 shows the on-chip memory access cycle.
φ or φ
Internal address bus
Internal read signal
Internal data bus
(read access)
Internal write signal
Internal data bus
(write access)
Basic Operational Timing
Access to On-Chip Memory (RAM, ROM)
SUB
Figure 2.11 On-Chip Memory Access Cycle
T
1
state
Bus cycle
Address
Rev. 7.00 Mar 10, 2005 page 55 of 652
Write data
Read data
T
2
state
SUB
). For details on these
REJ09B0042-0700
Section 2 CPU
SUB
to