hd64338023s Renesas Electronics Corporation., hd64338023s Datasheet - Page 371

• Manufacturer Part Number: hd64338023s
• Description: Renesas 8-bit Single-chip Microcomputer Super Low Power Series
• Manufacturer: Renesas Electronics Corporation.

Mode
Active (high-speed), sleep (high-speed)
Active (medium-speed), sleep (medium-speed) (φ/16)
f
Watch, subactive, subsleep, standby
φw = 32.768 kHz or 38.4 kHz *
Note: * Does not apply to H8/38124 Group.
3. When using the clock in the 16-bit mode, set CUEH to 1 first, then set CRCH to 1 in ECCSR.
4. When ECPWME in AEGSR is 1, event counter PWM is operating and therefore ECPWCRH,
5. The event counter PWM data register and event counter PWM compare register must be set so
6. As synchronization is established internally when an IRQAEC interrupt is generated, a
OSC
Or, set CUEH and CRCH simultaneously before inputting the clock. After that, do not change
the CUEH value while using in the 16-bit mode. Otherwise, an error counter increment may
occur. Also, to reset the counter, clear CRCH and CRCL to 0 simultaneously or clear CRCL
and CRCH to 0 sequentially, in that order.
ECPWCRL, ECPWDRH, and ECPWDRL should not be modified.
When changing the data, event counter PWM must be halted by clearing ECPWME to 0 in
AEGSR before modifying these registers.
that event counter PWM data register < event counter PWM compare register. If the settings
do not satisfy this condition, do not set ECPWME to 1 in AEGSR.
maximum error of 1 t
= 1 MHz to 4 MHz
cyc
will occur between clock halting and interrupt acceptance.
(φ/32)
(φ/64)
(φ/128)
(φw/2)
(φw/4)
(φw/8)
Rev. 7.00 Mar 10, 2005 page 329 of 652
Maximum AEVH/AEVL Pin Input
Clock Frequency
16 MHz
2 • f
f
1/2 • f
1/4 • f
1000 kHz
500 kHz
250 kHz
OSC
OSC
OSC
OSC
REJ09B0042-0700
Section 9 Timers