hd64338023s Renesas Electronics Corporation., hd64338023s Datasheet - Page 168

• Manufacturer Part Number: hd64338023s
• Description: Renesas 8-bit Single-chip Microcomputer Super Low Power Series
• Manufacturer: Renesas Electronics Corporation.

Section 5 Power-Down Modes
Bit 2
MSON
0
1
Bits 1 and 0—Subactive Mode Clock Select (SA1, SA0)
These bits select the CPU clock rate (φ
cannot be modified in subactive mode.
Bit 1
SA1
0
0
1
5.2
5.2.1
1. Transition to sleep (high-speed) mode
2. Transition to sleep (medium-speed) mode
Rev. 7.00 Mar 10, 2005 page 126 of 652
REJ09B0042-0700
The system goes from active mode to sleep (high-speed) mode when a SLEEP instruction is
executed while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON and DTON
bits in SYSCR2 are cleared to 0. In sleep mode CPU operation is halted but the on-chip
peripheral functions. CPU register contents are retained.
The system goes from active mode to sleep (medium-speed) mode when a SLEEP instruction
is executed while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in
SYSCR2 is set to 1, and the DTON bit in SYSCR2 is cleared to 0. In sleep (medium-speed)
mode, as in sleep (high-speed) mode, CPU operation is halted but the on-chip peripheral
functions are operational. The clock frequency in sleep (medium-speed) mode is determined
by the MA1 and MA0 bits in SYSCR1. CPU register contents are retained.
Furthermore, it sometimes acts with half state early timing at the time of transition to sleep
(medium-speed) mode.
Sleep Mode
Transition to Sleep Mode
Description
Operation in active (high-speed) mode
Operation in active (medium-speed) mode
Bit 0
SA0
0
1
*
Description
φ
φ
φ
W
W
W
/8
/4
/2
W
/2, φ
W
/4, or φ
W
/8) in subactive mode. SA1 and SA0
(initial value)
(initial value)
*: Don’t care