pef20550 Infineon Technologies Corporation, pef20550 Datasheet - Page 215

• Manufacturer Part Number: pef20550
• Description: Extended Line Card Interface Controller Elic
• Manufacturer: Infineon Technologies Corporation

Figure 66
ELIC
If DCL and FSC are selected as clock and framing signal source (CMD1:CSS = 1),
the CFI reference clock CRCL is obtained out of the DCL input signal after division by 1,
1.5 or 2 according to the prescaler selection (CMD1:CSP1 … 0). The CFI frame
structure is synchronized by the FSC input signal. Note that although the frequency and
phase of DCL and FSC may be chosen almost independently with respect to the
frequency and phase of PDC and PFS, the CFI clock source must still be synchronous
to the PCM interface clock source i.e. the two clock sources must always be derived from
one master clock. This mode must be selected if it is impossible to derive the required
CFI data rate from the PCM clock source. An overview of the different possibilities to
generate the PCM and CFI data and clock rates for CMD1:CSS = 1 is given in figure 67.
Semiconductor Group
DCL
FSC
®
Clock Sources for the CFI and PCM Interfaces if CMD1:CSS = 0
C
F
I
CMD2 : COC
*
Internal Reference
Clock (RCL)
Only CFI
Modes 0 and 3
M
U
X
CMD2 : FC2 ... 0
CFI Frame Sync.
CFI Data Rate
FC Modes 0-7
*
x2
CFI Mode
CFI Mode
0
3
0
3
2
1
2
1
Bit Shift
CTAR
CBSR : CDS2...0
÷2
÷2
÷4
CRCL
215
ELIC
R
CMD1 CSP1,
M
U
X
Bit Shift
POFU
POFD
PCSR
:
÷1.5
÷2
0
PMOD : PCR
PCM Frame Sync.
PCM Data Rate
M
U
X
Application Hints
÷2
PEB 20550
PEF 20550
ITS08045
P
C
M
PDC
PFS
01.96