pef20550 Infineon Technologies Corporation, pef20550 Datasheet - Page 286

• Manufacturer Part Number: pef20550
• Description: Extended Line Card Interface Controller Elic
• Manufacturer: Infineon Technologies Corporation

The 4 bit C/I channel can be accessed by the P for controlling layer-1 devices, or by
the ELIC arbiter to transmit the available/blocked information to the requesting HDLC
controller.
In upstream direction each change in the C/I value is reported by interrupt to the P and
the CFI time slot address is stored in the CIFIFO (refer to chapter 5.5.2). A C/I change
is detected if the value of the current CFI frame is different from the value of the previous
frame i.e. after, at most, 125 s.
To initialize two consecutive CFI timeslots for the arbiter D-Channel handling scheme,
the CM codes as given in table 43 must be used.
Table 43
Control Memory Codes and Data for the Arbiter D-Channel Handling Cheme
CM Address
Even timeslot downstream
Odd timeslot downstream
Even timeslot upstream
Odd timeslot upstream
Decentral D-Channel Handling Scheme
This option applies for IOM channels where the even timeslot consists of an 8 bit monitor
channel and the odd timeslot of a 2 bit D-Channel followed by a 4 bit C/I channel followed
by the 2 monitor handshake bits MR and MX.
The monitor channel is handled by the MF handler according to the selection of
handshake or non-handshake protocol. If the handshake option is selected (IOM-2), the
MF handler controls the MR and MX bits according to the IOM-2 specification. If the no
handshake option is selected (IOM-1), the MF handler sets both MR and MX bits to
logical 1; the MR and MX bit positions can then, if required, be accessed together with
the 4 bit C/I field via the even control memory address.
The D-Channel is not processed at all, i.e. the input in upstream direction is ignored and
the output in downstream direction is set to high impedance. External D-Channel
controllers, e.g. 2
order to realize decentral D-Channel processing.
The 4 bit C/I channel can be accessed by the µP for controlling layer-1 devices. In
upstream direction each change in the C/I value is reported by interrupt to the µP and the
CFI timeslot address is stored in the CIFIFO (refer to chapter 5.5.2). A C/I change is
detected if the value of the current CFI frame is different from the value of the previous
frame i.e. after at most 125 s.
Semiconductor Group
IDECs PEB 2075, can then be connected to each IOM interface in
CM Code
1010
1011
1000
0000
286
CM Data
11 C/I 11
XXXXXXXX
XX C/I XX
XXXXXXXX
B
Application Hints
B
B
B
PEB 20550
PEF 20550
01.96