pef20550 Infineon Technologies Corporation, pef20550 Datasheet - Page 304

• Manufacturer Part Number: pef20550
• Description: Extended Line Card Interface Controller Elic
• Manufacturer: Infineon Technologies Corporation

If the expected value ‘011101’ is actually received upon activation of the CFI (e.g.
OMDR = EEH), no interrupt will be generated at this moment. But the change detection
is now enabled and each valid change in the received SIG value (e.g. new value
‘001100’) will generate an interrupt, with the address being stored in the CIFIFO. The
reaction of the P to such an event would then look like this:
R:ISTA_E = 0100 0000
R:CIFIFO
W:MAAR
W:MACR
wait for STAR_E:MAC = 0
R:MADR
wait for further ISTA_E:SFI interrupts
5.5.3
If the configurable interface CFI of the ELIC is configured as IOM or SLD interface, it is
necessary to communicate with the connected subscriber circuits such as layer-1
transceivers (ISDN line cards) or codec filter devices (analog line cards) over the monitor
channel (IOM) or feature control channel (SLD). In order to simplify this task the ELIC
has implemented the Monitor/Feature Control (MF) Handler which autonomously
controls and supervises the data transfer via these channels.
The communication protocol used in an MF channel is interface and subscriber circuit
specific.
Three cases can be distinguished:
IOM
In this case the monitor channel protocol is a handshake procedure used for high speed
information exchange between the ELIC and other devices such as the IEC-Q
(PEB 2091), SBCX (PEB 2081) or SICOFI2 (PEB 2260).
The monitor channel operates on an asynchronous basis.While data transfers on the
IOM
by a handshake procedure based on the monitor channel receive (MR) and the monitor
channel transmit (MX) bits located at the end of the fourth timeslot of the respective
IOM
For the transmission of a data byte for example, the data is placed onto the downstream
monitor channel and the MX bit is activated. This byte will then be transmitted repeatedly
once per 8 kHz frame until the receiver acknowledges the transfer via the upstream MR
bit.
A detailed description of the IOM-2 monitor channel operation can be found in the
‘IOM-2 Interface Reference Guide’.
Semiconductor Group
®
-
-
2 interface take place synchronized to the IOM frame, the flow of data is controlled
2 channel.
-2 Interface Protocol
Monitor/Feature Control (MF) Handler
= 1001 1101
= 1001 1101
= 1100 1000
= 0011 00XX
B
B
B
B
B
; SFI interrupt
; address of upstream, port 2, timeslot 7
; copy the address from CIFIFO to MAAR
; read back command for CM DF, MOC = 1001
; read new SIG value (e.g. 001100)
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Application Hints
PEB 20550
PEF 20550
01.96