pef20550 Infineon Technologies Corporation, pef20550 Datasheet - Page 335

• Manufacturer Part Number: pef20550
• Description: Extended Line Card Interface Controller Elic
• Manufacturer: Infineon Technologies Corporation

The PICM register must be read after an ISTA_E:PIM interrupt in order to enable a new
PIM interrupt generation.
IPN:
TSN6 … 0:
Table 51
Identification of the Timeslot and Bit Number in Case of a Mismatch
PCM Mode
2
1, 3
0
Example
In PCM mode 1, the logical PCM port 0 is connected to two physical PCM transmission
links. The comparison function for RxD0/RxD1 is enabled via PMOD:AIC0 = 1. Suddenly
a bit error occurs at one of the receive lines in timeslot 13, bit 2. The P would then get
the following information from the ELIC:
Interrupt!
R: ISTA
R: PICM
In order to determine the line actually at fault (RxD0 or RxD1) the system must send a
known pattern in one of the timeslots and compare the actually received value with that
known pattern.
Semiconductor Group
= 04
= 13
Timeslot Identification
[TSN6 … 0 + 8]
[TSN6 … 1 + 4]
[TSN6 … 2 + 2]
H
H
Input Pair Number; this bit indicates the pair of input lines where a
mismatch occurred. A logical 0 indicates a mismatch between lines
RxD0 and RxD1, a logical 1 between lines RxD2 and RxD3.
Timeslot Number 6 … 0; these bits specify the timeslot number and
the bit positions that generated the ISTA_E:PIM interrupt according
to the table below. TPF denotes the number of timeslots per PCM
frame
; PIM interrupt
; IPN = 0, TSN6 … 1 = 9, TSN0 = 1
mod TPF
mod TPF
mod TPF
335
Bit Identification
TSN0 = 1 : bits 3 … 0
TSN0 = 0 : bits 7 … 4
TSN1 … 0 = 11 : bits 1 … 0
TSN1 … 0 = 10 : bits 3 … 2
TSN1 … 0 = 01 : bits 5 … 4
TSN1 … 0 = 00 : bits 7 … 6
Application Hints
PEB 20550
PEF 20550
01.96