peb3456e Infineon Technologies Corporation, peb3456e Datasheet - Page 149
peb3456e
Manufacturer Part Number
peb3456e
Description
Channelized T3 Termination, With Ds3 Framer, M13 Multiplexer, T1/e1 Framers And 256-channel Hdlc/ppp Controller
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEB3456E.pdf
(424 pages)
- Current page: 149 of 424
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•
Figure 5-2
5.2
Additional pins, which are not covered from the PCI specification, but are closely related,
are the SPI pins. Via the SPI pins the vendor ID and the vendor subsystem ID can be
loaded into the corresponding PCI configuration registers during start-up of the device.
The SPI Interface supports EEPROMs with an eight bit address space.
After a system reset, the TE3-CHATT starts reading the first byte out of the connected
EEPROM at address 00
memory contents. Everytime four bytes are read out of the EEPROM (starting with byte
address 01
space. The first four bytes will be written to the PCI configuration space address 00
next four bytes to the PCI configuration space address 04
of the EEPROM, starting with EEPROM byte address 01
configuration space after a system reset. During this configuration phase, all accesses
to the PCI interface will be answered with ‘retry’ by the PCI interface.
If the first byte in the EEPROM is not equal AA
the PCI configuration space immediately, and the PCI interface can be accessed. The
PCI configuration space in this case contains the default values.
The configuration mechanism through the serial interface can be disabled by pin
SPLOAD. If this pin is connected to ‘0’, the configuration mechanism is disabled. The
Data Sheet
DEVSEL
FRAME
TRDY
IRDY
C/BE
CLK
AD
H
SPI Interface (ROM Load Unit)
), the EEPROM interface writes the read information to the PCI configuration
PCI Write Transaction
1
Command
Address
Address
phase
2
H
. If this byte is equal AA
Data 1
BE 1
phase
Data
3
Data 2
BE 2
phase
Data
4
Bus transaction
149
H
H
, the EEPROM interface stops loading
5
, the device continues reading out the
BE 3
phase
H
Data
, will be mapped over the PCI
6
H
and so on. So the contents
Data 3
Interface Description
7
PEB 3456 E
8
05.2001
H
, the
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