peb3456e Infineon Technologies Corporation, peb3456e Datasheet - Page 47

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peb3456e

Manufacturer Part Number
peb3456e
Description
Channelized T3 Termination, With Ds3 Framer, M13 Multiplexer, T1/e1 Framers And 256-channel Hdlc/ppp Controller
Manufacturer
Infineon Technologies Corporation
Datasheet
3
3.1
TE3-CHATT
The TE3-CHATT is a highly integrated WAN protocol controller that performs HDLC,
PPP and transparent (TMA) protocol processing on 256 full duplex serial channels for a
channelized or unchannelized DS3 link. The device provides the framing functions for 28
T1 links or 21 E1 links. Signalling controller functions for DS3, T1 and E1 mode are
integrated as well.
The following operating modes are provided (assuming a PCI clock frequency of 33 MHz
or more):
• 28 times T1 signals operating at 1.544 MBit/s mapped into M13 asynchronous format
• 21 times E1 signals operating at 2.048 MBit/s mapped into ITU-T G.747 compliant
• Full payload rate DS3 signal in C-bit parity format
The serial interface operates in unipolar or dual-rail mode and connects directly to
available DS3 LIUs.
Each T1 or E1 tributary can be operated in external timing mode, where the tributary is
clocked with the common transmit clock CTCLK, or in looped timing mode, where data
of the selected tributaries is sent synchronous to the incoming receive clock.
A variety of loop modes is provided to support remote as well as inloop testing of the
device. Remote loops are provided on DS3-, DS2-, DS1- or payload level.
Two bus interfaces, a PCI Rev. 2.1 compliant bus interface and a 16 bit Intel/Motorola
style bus interface, connect the device to system environment. Device configuration and
channel operation is provided through the PCI bus interface, whereas the 16 bit bus
interface provides access to the framing functions and the signalling controller. The TE3-
CHATT supports PCI PnP capability by loading the subsystem ID and the subsystem
vendor ID via a SPI
Data Sheet
or C-bit parity format
signal.
General Overview
Functional Overview
TM
interface into the PCI configuration space.
47
General Overview
PEB 3456 E
05.2001

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