peb3456e Infineon Technologies Corporation, peb3456e Datasheet - Page 291
peb3456e
Manufacturer Part Number
peb3456e
Description
Channelized T3 Termination, With Ds3 Framer, M13 Multiplexer, T1/e1 Framers And 256-channel Hdlc/ppp Controller
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEB3456E.pdf
(424 pages)
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D3RFEBEC
DS3 Receive FEBE Error Counter
Access
Address
Reset Value
FEBEC(15:0) FEBE error events
D3REXZ
DS3 Receive Excessive Zeroes Counter
Access
Address
Reset Value
EXZ(15:0)
Data Sheet
15
15
: read/write
: 1F0
: 0000
Error counter mode (Clear on Read or Errored Second) depends on
register D3RCFG.ECM.
This register counts the occurence of a received ‘not all ‘1’s’. FEBE-bits
are triplicated in the DS3 frame structure but only one single error
maximum is counted per multiframe. Errors are not counted in out of
frame state.
: read/write
: 1F4
: 0000
Exzessive Zeroes
Error counter mode (Clear on Read or Errored Second) depends on
register D3RCFG.ECM.
Violations are 3 zero strings. The error counter will not be incremented
during asynchronous state.
H
H
H
H
(PCI), 78
(PCI), 7A
H
H
(Local bus)
(Local bus)
FEBE(15:0)
EXZ(15:0)
291
Register Description
PEB 3456 E
05.2001
0
0
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