peb3456e Infineon Technologies Corporation, peb3456e Datasheet - Page 15
![no-image](/images/no-image-200.jpg)
peb3456e
Manufacturer Part Number
peb3456e
Description
Channelized T3 Termination, With Ds3 Framer, M13 Multiplexer, T1/e1 Framers And 256-channel Hdlc/ppp Controller
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PEB3456E.pdf
(424 pages)
- Current page: 15 of 424
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List of Figures
Figure 1-1
Figure 1-2
Figure 2-1
Figure 3-1
Figure 4-1
Figure 4-2
Figure 4-3
Figure 4-4
Figure 4-5
Figure 4-6
Figure 4-7
Figure 4-8
Figure 4-9
Figure 4-10
Figure 4-11
Figure 4-12
Figure 4-13
Figure 4-14
Figure 4-15
Figure 4-16
Figure 4-17
Figure 4-18
Figure 4-19
Figure 5-1
Figure 5-2
Figure 5-3
Figure 5-4
Figure 5-5
Figure 5-6
Figure 5-7
Figure 5-8
Figure 5-9
Figure 5-10
Figure 5-11
Figure 8-1
Figure 8-2
Figure 8-3
Figure 8-4
Figure 8-5
Figure 8-6
Data Sheet
124
137
TE3-CHATT Logic Symbol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
System Integration of the TE3-CHATT . . . . . . . . . . . . . . . . . . . . . . . . 26
TE3-CHATT Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
TE3-CHATT Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Port configuration in M13 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Local Port Loops in M13 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Remote Line Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Test Breakout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Time slot Assignment in Channelized Modes . . . . . . . . . . . . . . . . . . . 58
Descriptor Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Receive Buffer Thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Transmit Buffer Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
HDLC Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Bit Synchronous PPP with HDLC Framing Structure. . . . . . . . . . . . . . 77
CRC-4 Multiframe Alignment Recovery Algorithms . . . . . . . . . . . . . . . 95
Interrupt Driven Reception Sequence Example . . . . . . . . . . . . . . . . . 107
Interrupt Driven Transmit Sequence Example . . . . . . . . . . . . . . . . . . 108
Test Unit Access Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Pattern Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Mailbox Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Layer Two Interrupts (Channel, command, port and system interrupts . . .
Interrupt Queue Structure in System Memory . . . . . . . . . . . . . . . . . . 125
Framer, M13 and Facility Data Link and Mailbox Interrupt Notification . . .
PCI Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
PCI Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
SPI Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
SPI Write Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Intel Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Intel Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Motorola Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Motorola Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Receive Overhead Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Transmit Overhead Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Block Diagram of Test Access Port and Boundary Scan Unit . . . . . . 161
DS3 Transmit Overhead Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
DS3 Transmit Overhead Synchronization Timing . . . . . . . . . . . . . . . 215
DS3 Receive Overhead Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
DS3 Transmit Stuff Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
DS3 Receive Stuff Bit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
T1/E1 Tributary Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 215
15
PEB 3456 E
05.2001
Page
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