tmp89fm43l TOSHIBA Semiconductor CORPORATION, tmp89fm43l Datasheet - Page 185

• Manufacturer Part Number: tmp89fm43l
• Description: 8 Bit Microcontroller Tlcs-870/c1 Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

RB002
13.4.6.3
(1)
(2)
Register buffer configuration
TA0DRAL (TA0DRBL), the data is first stored into this temporary buffer, whether the double buffer
is enabled or disabled. Subsequently, when a write instruction is executed on TA0DRAH (TA0DRBH),
the set value is stored into the double buffer or TA0DRAH (TA0DRBH). At the same time, the set value
in the temporary buffer is stored into the double buffer or TA0DRAL (TA0DRBL). (This structure is
designed to enable the set values of the lower-level register and the higher-level register simultaneously.)
Therefore, when setting data to TA0DRA (TA0DRB), be sure to write the data into TA0DRAL and
TA0DRAH (TA0DRBL and TA0DRBH) in this order.
TA0CR<TA0DBF> to "0" disables the double buffer. Setting TA0CR<TA0DBF> to "1" enables the
double buffer.
The TMP89FM43L contains an 8-bit temporary buffer. When a write instruction is executed on
See Figure 13-1 for the temporary buffer configuration.
In the TMP89FM43L, the double buffer can be used by setting TA0CR<TA0DBF>. Setting
See Figure 13-1 for the double buffer configuration.
Temporary buffer
Double buffer
-
-
When the double buffer is enabled
the set value is first stored into the double buffer, and TA0DRAH/L are not updated immedi-
ately. TA0DRAH/L (TA0DRBH/L) compare the last set values to the counter value. If a match
is detected, an INTTCA0 interrupt request is generated and the double buffer set value is stored
into TA0DRAH/L (TA0DRBH/L). Subsequently, the match detection is executed using a new
set value.
value (the last set value) is read, not the TA0DRAH/L (TA0DRBH/L) values (the current
effective values).
stopped, the set value is immediately stored into both the double buffer and TA0DRAH/L
(TA0DRBH/L).
When the double buffer is disabled
the set value is immediately stored in TA0DRAH/L (TA0DRBH/L). Subsequently, the match
detection is executed using a new set value.
up counter overflows and the match detection is executed using a new set value. As a result,
the output pulse width may be longer than the set time. If that is a problem, enable the double
buffer.
stopped, the set value is immediately stored into TA0DRAH/L (TA0DRBH/L).
When a write instruction is executed on TA0DRAH (TA0DRBH) during the timer operation,
When a read instruction is executed on TA0DRAH/L (TA0DRBH/L), the double buffer
When a write instruction is executed on TA0DRAH/L (TA0DRBH/L) while the timer is
When a write instruction is executed on TA0DRAH (TA0DRBH) during the timer operation,
If the values set to TA0DRAH/L (TA0DRBH/L) are smaller than the up counter value, the
When a write instruction is executed on TA0DRAH/L (TA0DRBH/L) while the timer is
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TMP89FM43L