tmp89fm43l TOSHIBA Semiconductor CORPORATION, tmp89fm43l Datasheet - Page 300

• Manufacturer Part Number: tmp89fm43l
• Description: 8 Bit Microcontroller Tlcs-870/c1 Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

18.4
Functions
RA002
18.4.5
18.4.6
18.4.7
arbitration lost is detected, SBI0CR2<MST> is cleared to "0" by the hardware.
SBI0CR2<TRX> should be cleared to "0".
bit (R/W) sent from the master device is "1", and is cleared to "0" if the bit is "0".
to "0" by hardware if a transmitted direction bit is "1", and is set to "1" by hardware if it is "0". When an
acknowledge signal is not returned, the current condition is maintained.
hardware. Table 18-3 shows SBI0CR2<TRX> changing conditions in each mode and SBI0CR2<TRX> value
after changing.
recognized. They are handled as data just after generating the start condition. SBI0CR2<TRX> is not changed
by the hardware.
a bus after generating a start condition by writing "1" to SBI0CR2 <MST>, SBI0CR2<TRX>, SBI0CR2<BB>
and SBI0CR2<PIN>. It is necessary to set SBI0CR1<ACK> to "1" before generating the start condition.
To set a master device, SBI0CR2<MST> should be set to "1".
To set a slave device, SBI0CR2<MST> should be cleared to "0". When a stop condition on the bus or an
To set the device as a transmitter, SBI0CR2<TRX> should be set to "1". To set the device as a receiver,
For the I
In the master mode, after an acknowledge signal is returned from the slave device, SBI0CR2<TRX> is cleared
When a stop condition on the bus or an arbitration lost is detected, SBI0CR2<TRX> is cleared to "0" by the
When the serial bus interface circuit operates in the free data format, a slave address and a direction bit are not
When SBI0SR2<BB> is "0", a slave address and a direction bit which are set to the SBI0DBR are output on
level. After detecting this situation, Master 2 resets counting a clock pulse in the high level and sets the SCL
pin to the low level.
Since Master 2 holds the SCL line of the bus at the low level, Master 1 waits for counting a clock pulse in
the high level. After Master 2 sets a clock pulse to the high level at point "c" and detects the SCL line of the
bus at the high level, Master 1 starts counting a clock pulse in the high level. Then, the master, which has
finished the counting a clock pulse in the high level, pulls down the SCL pin to the low level.
master device with the longest low-level period from among those master devices connected to the bus.
Master/slave selection
Transmitter/receiver selection
Start/stop condition generation
Note:When SBI0CR1<NOACK> is "1", the slave address match detection and the GENERAL CALL detection
As Master 1 pulls down the SCL pin to the low level at point "a", the SCL line of the bus becomes the low
Master 1 finishes counting a clock pulse in the low level at point "b" and sets the SCL pin to the high level.
The clock pulse on the bus is determined by the master device with the shortest high-level period and the
Table 18-3 SBI0CR1<TRX> Operation in Each Mode
Slave mode
are disabled, and thus SBI0CR2<TRX> remains unchanged.
2
Master
Mode
mode
C bus data transfer in the slave mode, SBI0CR2<TRX> is set to "1" by the hardware if the direction
Direction bit
"0"
"1"
"0"
"1"
A received slave address is the
same as the value set to
I2C0AR<SA>
ACK signal is returned
Page 286
Changing condition
TRX after changing
"0"
"1"
"1"
"0"
TMP89FM43L