tmp89fm43l TOSHIBA Semiconductor CORPORATION, tmp89fm43l Datasheet - Page 49

• Manufacturer Part Number: tmp89fm43l
• Description: 8 Bit Microcontroller Tlcs-870/c1 Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

RB000
2.3.6.4
(1)
(2)
(1)
The SLOW mode is controlled by system control register 2 (SYSCR2).
SLOW mode
TBTCR<TBTCK> is detected. After the IDLE0 or SLEEP0 mode is released, the operation is restarted
by the instruction that follows the IDLE0 or SLEEP0 mode start instruction.
TBTCR<TBTCK> is detected. After the release, the INTTBT interrupt processing is started.
system clock (fm) is switched to fs/4.
off the high-frequency clock oscillator.
up counter before implementing the procedure described above.
Note 1: The IDLE0 or SLEEP0 mode is released to the NORMAL1 or SLOW1 mode by the asynchronous
Note 2: When a watchdog timer interrupt is generated immediately before the IDLE0 or SLEEP0 mode is
Note 1: Be sure to follow this procedure to switch the operation from the NORMAL2 mode to the SLOW1
Note 2: It is also possible to allow the basic clock for the high-frequency clock to oscillate continuously to
Note 3: After switching SYSCR2<SYSCK>, be sure to wait for 2 machine cycles or longer before clearing
Note 4: When the main system clock (fm) is switched, the gear clock (fcgck) is synchronized with the clock
The IDLE0 or SLEEP0 mode is released when the falling edge of the source clock selected at
When TBTCR<TBTEN> is "1", the time base timer interrupt latch is set.
The IDLE0 or SLEEP0 mode is released when the falling edge of the source clock selected at
Set SYSCR2<SYSCK> to "1".
When a maximum of 2/fcgck + 10/fs [s] has elapsed since SYSCR2<SYSCK> is set to "1", the main
After switching, wait for 2 machine cycles or longer, and then clear SYSCR2<XEN> to "0" to turn
If the oscillation of the low-frequency clock (fs) is unstable, confirm the stable oscillation at the warm-
Normal release mode (IMF, EF5, TBTCR<TBTEN> = "0")
Interrupt release mode (IMF, EF5, TBTCR<TBTEN> = "1")
Switching from the NORMAL2 mode to the SLOW1 mode
internal clock selected at TBTCR<TBTCK>. Therefore, the period from the start to the release of
the mode may be shorter than the time specified at TBTCR<TBTCK>.
started, the watchdog timer interrupt will be processed but the IDLE0 or SLEEP0 mode will not be
started.
mode.
return to NORMAL2 mode. However, be sure to turn off the oscillation of the basic clock for the
high-frequency clock when the STOP mode is started from the SLOW mode.
SYSCR2<XEN> to "0". Clearing it within 2 machine cycles causes a system clock reset.
that is a quarter of the basic clock (fs) for the low-frequency clock. For the synchronization, fm is
stopped for a period of 10/fs or shorter.
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TMP89FM43L