pxf4336 Infineon Technologies Corporation, pxf4336 Datasheet - Page 231
pxf4336
Manufacturer Part Number
pxf4336
Description
Abm Premium Atm Buf Fer Manager
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PXF4336.pdf
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7.2.9
Register 31 DSBT1
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Bit
Bit
DSBT1HP(11:4)
DSBT1LP(11:4)
Data Sheet
15
7
DBA Control Registers
Upstream/Downstream DBA Scheduler Block Threshold Register 1
14
DBA Scheduler Block Threshold 1 High Priority
This bit field represents the most significant 8 bits of the internal
12-bit wide High Priority DBA Threshold 1. The threshold value is
global, but individually evaluated against all scheduler block
specific fill level counter (upstream and downstream) of the same
priority class (SBOccHP).
The threshold range is (0..4095) with a granularity of 16 cells.
The CPU programs the threshold with a granularity of 4 cells by
right shifting the value by 4:
DSBT1HP(11:4):= (threshold_value >> 4)
DBA Scheduler Block Threshold 1 Low Priority
This bit field represents the most significant 8 bits of the internal
12-bit wide Low Priority DBA Threshold 1. The threshold value is
global, but individually evaluated against all scheduler block
specific fill level counter (upstream and downstream) of the same
priority class (SBOccLP).
The threshold range is (0..4095) with a granularity of 16 cells.
The CPU programs the threshold with a granularity of 4 cells by
right shifting the value by 4:
DSBT1LP(11:4):= (threshold_value >> 4)
6
Read/Write
FFFF
DSBT1
Written and Read by CPU during initialization
H
13
5
36
DSBT1HP(11:4)
H
DSBT1LP(11:4)
12
4
231
11
3
10
2
Register Description
PXF 4336 V1.1
9
1
2001-12-17
ABM-P
8
0
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