pxf4336 Infineon Technologies Corporation, pxf4336 Datasheet - Page 343

• Manufacturer Part Number: pxf4336
• Description: Abm Premium Atm Buf Fer Manager
• Manufacturer: Infineon Technologies Corporation

Register 104 PLL2CONF
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Bit
Bit
DPLL2 generates a clock that is an alternative clock source for the ERC unit. The
DPLL2 is fed by clock input signal ‘SYSCLK’. Signal ‘IOPCLKSEL’ determines the clock
source of the ERC unit.
details.
Locked2
Div1En2
Data Sheet
Locked2 unused
15
7
M2(1:0)
PLL2 Configuration Register
14
DPLL2 Locked
(read only)
1
0
Division Factor 1 Enable for DPLL2
This bit enables the additional divide by 2 factor subsequent to the
DPLL2 output.
0
1
6
Read/Write
0000
PLL2CONF
Written and Read by CPU
Section 3.2.7 “Clocking System” on Page 55
H
Dev1En
13
2
5
DPLL2 is locked based on the current parameter
setting.
DPLL2 is in transient status.
Division Factor 1 disabled.
Division Factor 1 enabled.
D8
BYPAS
H
12
S2
4
343
PU2
11
3
N2(5:0)
RES2
10
2
Register Description
PXF 4336 V1.1
9
1
provides the
M2(3:2)
2001-12-17
ABM-P
8
0