pxf4336 Infineon Technologies Corporation, pxf4336 Datasheet - Page 57

• Manufacturer Part Number: pxf4336
• Description: Abm Premium Atm Buf Fer Manager
• Manufacturer: Infineon Technologies Corporation

Figure 3-8
The division factor determined by m must be chosen such that intermediate frequency
f
The multiplication factor determined by n must be chosen such that intermediate
frequency f
final value in case of DPLL1.
Finally, the division by the two factors (f
or two divisions by the two factors (f
final clock frequency.
When choosing the factors m and n, two conditions must be met:
• n=1..24: f
• f
3.2.7.3
The following numbers are assumed for this example:
• ABM-P internal core clock: 52 MHz
• ABM-P ERC clock: 60 MHz
• Clock supply: 52 MHz at signal SYSCLK
Data Sheet
1
Register PLL1CONF
Lockedi Div2Eni Div1Eni Bypassi
is in the range 2..15 MHz based on the input frequency at signal ‘SYSCLK’.
15
n=25..63: f
2
f
in
must be in a range of 100 to 200 MHz
X
2
Programming Example
(0)
1
is equal or twice the final value in case of DPLL2 and twice or four times the
(1)
must be in a range of 5..15 MHz
1
DPLL Structure
must be in a range of 2..6 MHz
(m + 1)
1
PUi
f
1
RESi
=
2..15 MHz
f
in
f
⁄
1
(
m
1
,f
+
2
) may be enabled in case of DPLL1 to achieve the
1
Mi(3:0)
)
1
,f
2
(n + 1)
57
) may be enabled in case of DPLL2 and one
;
f
2
=
f
f
2
in
×
X
(0)
--------------
m
(1)
n
+
+
1
1/2
1
Functional Description
Ni(5:0)
X
(0)
(1)
PXF 4336 V1.1
1/2
2001-12-17
0
ABM-P
f
out