lpc2917 NXP Semiconductors, lpc2917 Datasheet - Page 24

• Manufacturer Part Number: lpc2917
• Description: Arm9 Microcontroller With Can And Lin
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2917_19_1
Preliminary data sheet
8.4.2.1 Overview
8.4.2.2 Description
8.4.2.3 Pin description
8.4.2.4 Watchdog timer clock description
8.4.3.1 Overview
8.4.2 Watchdog timer
8.4.3 Timer
The purpose of the watchdog timer is to reset the ARM9 processor within a reasonable
amount of time if the processor enters an error state. The watchdog generates a system
reset if the user program fails to trigger it correctly within a predetermined amount of time.
Key features:
The watchdog timer consists of a 32-bit counter with a 32-bit prescaler.
The watchdog should be programmed with a time-out value and then periodically
restarted. When the watchdog times out it generates a reset through the RGU.
To generate watchdog interrupts in watchdog debug mode the interrupt has to be enabled
via the interrupt enable register. A watchdog-overflow interrupt can be cleared by writing
to the clear-interrupt register.
Another way to prevent resets during debug mode is via the Pause feature of the
Watchdog Timer. The watchdog is stalled when the ARM9 is in debug mode and the
PAUSE_ENABLE bit in the Watchdog Timer Control register is set.
The Watchdog Reset output is fed to the Reset Generator Unit (RGU). The RGU contains
a reset source register to identify the reset source when the device has gone through a
reset. See
The watchdog has no external pins.
The Watchdog Timer is clocked by two different clocks; CLK_SYS_PESS and
CLK_SAFE, see
by CLK_SYS_PESS. The timer and prescale counters are clocked by CLK_SAFE which
is always on.
The LPC2917/19 contains six identical timers: four in the peripheral subsystem and two in
the Modulation and Sampling Control SubSystem (MSCSS) located at different peripheral
base addresses. This section describes the four timers in the peripheral subsystem. Each
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CLK_SAFE see
Internal chip reset if not periodically triggered
Timer counter register runs on always-on safe clock
Optional interrupt generation on watchdog timeout
Debug mode with disabling of reset
Watchdog control register change-protected with key
Programmable 32-bit watchdog timer period with programmable 32-bit prescaler.
Section
Section
8.8.5.
Rev. 1.01 — 15 November 2007
Section 7.2.2
7.2.2. The register interface towards the system bus is clocked
ARM9 microcontroller with CAN and LIN
LPC2917/19
© NXP B.V. 2007. All rights reserved.
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