lpc2917 NXP Semiconductors, lpc2917 Datasheet - Page 23

• Manufacturer Part Number: lpc2917
• Description: Arm9 Microcontroller With Can And Lin
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2917_19_1
Preliminary data sheet
8.3.4.2 Description
8.3.4.3 Event-router pin description and mapping to register bit positions
8.4.1 Peripheral subsystem clock description
8.4 Peripheral subsystem
The event router allows the event source to be defined, its polarity and activation type to
be selected and the interrupt to be masked or enabled. The event router can be used to
start a clock on an external event.
The vectored interrupt-controller inputs are active HIGH.
The event router module in the LPC2917/19 is connected to the pins listed below. The
pins are combined with other functions on the port pins of the LPC2917/19.
shows the pins connected to the event router, and also the corresponding bit position in
the event-router registers and the default polarity.
Table 13.
The peripheral subsystem is clocked by a number of different clocks:
Symbol
EXTINT0
EXTINT1
EXTINT2
EXTINT3
EXTINT4
EXTINT5
EXTINT6
EXTINT7
CAN0 RXD
CAN1 RXD
-
LIN0 RXD
LIN1 RXD
-
-
-
-
-
•
•
•
•
•
Event detection is fully asynchronous, so no clock is required
CLK_SYS_PESS
CLK_UART0/1
CLK_SPI0/1/2
CLK_TMR0/1/2/3
Event-router pin connections
Direction
in
in
in
in
in
in
in
in
in
in
-
in
in
-
na
na
na
-
Rev. 1.01 — 15 November 2007
Bit position
0
1
2
3
4
5
6
7
8
9
13 - 10
14
15
21 - 16
22
23
24
26 - 25
Description
external interrupt input 0
external interrupt input 1
external interrupt input 2
external interrupt input 3
external interrupt input 4
external interrupt input 5
external interrupt input 6
external interrupt input 7
CAN0 receive data input wake-up
CAN1 receive data input wake-up
LIN0 receive data input wake-up
LIN1 receive data input wake-up
CAN interrupt (internal)
VIC FIQ (internal)
VIC IRQ (internal)
reserved
reserved
reserved
ARM9 microcontroller with CAN and LIN
LPC2917/19
© NXP B.V. 2007. All rights reserved.
Table 13
Default
polarity
1
1
1
1
1
1
1
1
0
0
-
0
0
-
1
1
1
-
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