str912fa STMicroelectronics, str912fa Datasheet - Page 12

• Manufacturer Part Number: str912fa
• Description: Arm966e-s? 16/32-bit Flash Mcu With Ethernet, Usb, Can, Ac Motor Control, 4 Timers, Adc, Rtc, Dma
• Manufacturer: STMicroelectronics

Functional overview
2.9
2.9.1
2.9.2
Note:
12/78
values indicating memory size or other differentiating features. Byte 30 contains the silicon
revision level indicator. See
devices. See the Errata Sheet documents for STR91xF and STR91xFA for details of external
identification of silicon revisions.
Table 2.
Vectored interrupt controller (VIC)
Interrupt management in the STR91xFA is implemented from daisy-chaining two standard ARM
VIC units. This combined VIC has 32 prioritized interrupt request channels and generates two
interrupt output signals to the CPU. The output signals are FIQ and IRQ, with FIQ having higher
priority.
FIQ handling
FIQ (Fast Interrupt reQuest) is the only non-vectored interrupt and the CPU can execute an
Interrupt Service Routine (ISR) directly without having to determine/prioritize the interrupt
source, minimizing ISR latency. Typically only one interrupt source is assigned to FIQ. An FIQ
interrupt has its own set of banked registers to minimize the time to make a context switch. Any
of the 32 interrupt request input signals coming into the VIC can be assigned to FIQ.
IRQ handling
IRQ is a vectored interrupt and is the logical OR of all 32 interrupt request signals coming into
the 32 IRQ channels. Priority of individual vectored interrupt requests is determined by
hardware (IRQ channel Intr 0 is highest priority, IRQ channel Intr 31 is lowest).
However, inside the same VIC (primary or secondary VIC), CPU firmware may re-assign
individual interrupt sources to individual hardware IRQ channels, meaning that firmware can
effectively change interrupt priority levels as needed within the same VIC (from priority 0 to
priority 16).
Note: VIC0 (primary VIC) interrupts always have higher priority than VIC1 (secondary VIC)
interrupts
When the IRQ signal is activated by an interrupt request, VIC hardware will resolve the IRQ
interrupt priority, then the ISR reads the VIC to determine both the interrupt source and the
vector address to jump to the service code.
The STR91xFA has a feature to reduce ISR response time for IRQ interrupts. Typically, it
requires two memory accesses to read the interrupt vector address from the VIC, but the
STR91xFA reduces this to a single access by adding a 16th entry in the instruction branch
cache, dedicated for interrupts. This 16th cache entry always holds the instruction that reads
the interrupt vector address from the VIC, eliminating one of the memory accesses typically
required in traditional ARM implementations.
Production salestype
STR91xFAxxxxx
STR91xFxxxxx
Product ID and revision level values
Table 2
Silicon revision
Rev G
Rev D
for values related to the two revisions of STR9 production
OTP byte 31
91h
91h
OTP byte 30
03h
20h
STR91xFA