str912fa STMicroelectronics, str912fa Datasheet - Page 24

• Manufacturer Part Number: str912fa
• Description: Arm966e-s? 16/32-bit Flash Mcu With Ethernet, Usb, Can, Ac Motor Control, 4 Timers, Adc, Rtc, Dma
• Manufacturer: STMicroelectronics

Functional overview
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the host computer must have a static image of the code being executed for decompressing the
ETM9 data. Because of this, self-modified code cannot be traced.
Ethernet MAC interface with DMA
STR91xFA devices in 128-pin and 144-ball packages provide an IEEE-802.3-2002 compliant
Media Access Controller (MAC) for Ethernet LAN communications through an industry
standard Medium Independent Interface (MII). The STR91xFA requires an external Ethernet
physical interface device (PHY) to connect to the physical LAN bus (twisted-pair, fiber, etc.).
The PHY is connected to the STR91xFA MII port using as many as 18 signals (see pins which
have signal names MII_* in
The MAC corresponds to the OSI Data Link layer and the PHY corresponds to the OSI Physical
layer. The STR91xFA MAC is responsible for:
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The STR91xFA MAC includes the following features:
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A 32-bit burst DMA channel residing on the AHB is dedicated to the Ethernet MAC for high-
speed data transfers, side-stepping the CPU for minimal CPU impact during transfers. This
DMA channel includes the following features:
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USB 2.0 slave device interface with DMA
The STR91xFA provides a USB slave controller that implements both the OSI Physical and
Data Link layers for direct bus connection by an external USB host on pins USBDP and
USBPN. The USB interface detects token packets, handles data transmission and reception,
and processes handshake packets as required by the USB 2.0 standard.
The USB slave interface includes the following features:
Data encapsulation, including frame assembly before transmission, and frame parsing/
error detection during and after reception.
Media access control, including initiation of frame transmission and recover from
transmission failure.
Supports 10 and 100 Mbps rates
Tagged MAC frame support (VLAN support)
Half duplex (CSMA/CD) and full duplex operation
MAC control sublayer (control frames) support
32-bit CRC generation and removal
Several address filtering modes for physical and multicast address (multicast and group
addresses)
32-bit status code for each transmitted or received frame
Internal FIFOs to buffer transmit and receive frames. Transmit FIFO depth is 4 words (32
bits each), and the receive FIFO is 16 words deep.
Direct SRAM to MAC transfers of transmit frames with the related status, by descriptor
chain
Direct MAC to SRAM transfers of receive frames with the related status, by descriptor
chain
Open and Closed descriptor chain management
Table
5).
STR91xFA