str912fa STMicroelectronics, str912fa Datasheet - Page 19

• Manufacturer Part Number: str912fa
• Description: Arm966e-s? 16/32-bit Flash Mcu With Ethernet, Usb, Can, Ac Motor Control, 4 Timers, Adc, Rtc, Dma
• Manufacturer: STMicroelectronics

STR91xFA
2.13
Note:
2.13.1 Supply voltage brownout
2.13.2 Supply voltage dropout
2.13.3 Watchdog timer
System supervisor
The STR91xFA monitors several system and environmental inputs and will generate a global
reset, a system reset, or an interrupt based on the nature of the input and configurable settings.
A global reset clears all functions on the STR91xFA, a system reset will clear all but the Clock
Control Unit (CCU) settings and the system status register. At any time, firmware may reset
individual on-chip peripherals. System supervisor inputs include:
●
●
●
●
●
●
GR: means the input causes Global Reset, SR: means the input causes System Reset
The CPU may read a status register after a reset event to determine if the reset was caused by
a watchdog timer timeout or a voltage supply drop out. This status register is cleared only by a
power up reset.
Each operating voltage source (V
Detect (LVD) circuitry. The LVD will generate an early warning interrupt to the CPU when
voltage sags on either V
applications because the system can perform an orderly shutdown before the batteries become
too weak. The voltage trip point to cause a brown out interrupt is typically 0.25V above the LVD
dropout thresholds that cause a reset.
CPU firmware may prevent all brown-out interrupts by writing to interrupt mask registers at run-
time.
LVD circuitry will always cause a global reset if the CPU’s V
threshold of 1.4V.
However, the LVD trigger threshold to cause a global reset for the I/O ring’s V
to one of two different levels, depending if V
3.0V to 3.6V. If V
V
by STR91xFA device configuration software from STMicroelectronics or IDE from 3rd parties,
and is programmed into the STR91xFA device along with other configurable items through the
JTAG interface when the Flash memory is programmed.
CPU firmware may prevent some LVD resets if desired by writing a control register at run-time.
Firmware may also disable the LVD completely for lowest-power operation when an external
LVD device is being used.
The STR91xFA has a 16-bit down-counter (not one of the four TIM timers) that can be used as
a watchdog timer or as a general purpose free-running timer/counter. The clock source is the
DDQ
GR: CPU voltage supply (V
GR: I/O voltage supply (V
GR: Power-Up condition
SR: Watchdog timer timeout
SR: External reset pin (RESET_INn)
SR: JTAG debug reset command
operation is 3.0V and 3.6V, the LVD threshold is 2.7V. The choice of trigger level is made
DDQ
operation is at 2.7V to 3.3V, the LVD dropout trigger threshold is 2.4V. If
DD
or V
DDQ
DDQ
DD
DD
) drop out or brown out
) drop out or brown out
voltage inputs. This is an advantage for battery powered
and V
DDQ
DDQ
) is monitored separately by the Low Voltage
will be operated in the range of 2.7V to 3.3V, or
DD
source drops below it’s fixed
Functional overview
DDQ
source is set
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