str912fa STMicroelectronics, str912fa Datasheet - Page 16

• Manufacturer Part Number: str912fa
• Description: Arm966e-s? 16/32-bit Flash Mcu With Ethernet, Usb, Can, Ac Motor Control, 4 Timers, Adc, Rtc, Dma
• Manufacturer: STMicroelectronics

Functional overview
2.10.6 Baud rate clock (BRCLK)
2.10.7 External memory interface bus clock (BCLK)
2.10.8 USB interface clock
2.10.9 Ethernet MAC clock
2.10.10 External RTC calibration clock
2.10.11 Operation example
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between the ARM core and the Flash memory. Typically, codes in the Flash memory can be
fetched one word per FMICLK clock in burst mode. The maximum FMICLK frequency is
96MHz.
The baud rate clock is an internal clock derived from f
UART peripherals for baudrate generation. The frequency can be optionally divided by 2.
The BCLK is an internal clock that controls the EMI bus. All EMI bus signals are synchronized
to the BCLK. The BCLK is derived from the HCLK and the frequency can be configured to be
the same or half that of the HCLK. Refer to
frequency (f
Special consideration regarding the USB interface: The clock to the USB interface must operate
at 48 MHz and comes from one of three sources, selected under firmware control:
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Special consideration regarding the Ethernet MAC: The external Ethernet PHY interface device
requires it’s own 25 MHz clock source. This clock can come from one of two sources:
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The RTC_CLK can be enabled as an output on the JRTCK pin. The RTC_CLK is used for RTC
oscillator calibration. The RTC_CLK is active in Sleep mode and can be used as a system wake
up control clock.
As an example of CCU operation, a 25 MHz crystal can be connected to the main oscillator
input on pins X1_CPU and X2_CPU, a 32.768 kHz crystal connected to pins X1_RTC and
X2_RTC, and the clock input of an external Ethernet PHY device is connected to STR91xFA
output pin P5.2. In this case, the CCU can run the CPU at 96 MHz from PLL, the USB interface
CCU master clock output of 48 MHz.
CCU master clock output of 96 MHz. An optional divided-by-two circuit is available to
produce 48 MHz for the USB while the CPU system runs at 96MHz.
STR91xFA pin P2.7. An external 48 MHz oscillator connected to pin P2.7 can directly
source the USB while the CCU master clock can run at some frequency other than 48 or
96 MHz.
A 25 MHz clock signal coming from a dedicated output pin (P5.2) of the STR91xFA. In this
case, the STR91xFA must use a 25 MHz signal on its main oscillator input in order to pass
this 25 MHz clock back out to the PHY device through pin P5.2. The advantage here is that
an inexpensive 25 MHz crystal may be used to source a clock to both the STR91xFA and
the external PHY device.
An external 25 MHz oscillator connected directly to the external PHY interface device. In
this case, the STR91xFA can operate independent of 25 MHz.
BCLK
). The BCLK clock is available on the LFBGA package as an output pin.
Table 12 on page 53
MSTR
that is used by the three on-chip
for the maximum BCLK
STR91xFA