mc9s08gt32a Freescale Semiconductor, Inc, mc9s08gt32a Datasheet - Page 180

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mc9s08gt32a

Manufacturer Part Number
mc9s08gt32a
Description
Hcs08 Microcontrollers 8-bit Microcontroller Family
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Serial Communications Interface (S08SCIV1)
11.2.7
This register is actually two separate registers. Reads return the contents of the read-only receive data
buffer and writes go to the write-only transmit data buffer. Reads and writes of this register are also
involved in the automatic flag clearing mechanisms for the SCI status flags.
180
Reset
Field
ORIE
NEIE
FEIE
PEIE
3
2
1
0
W
R
SCI Data Register (SCIxD)
Overrun Interrupt Enable — This bit enables the overrun flag (OR) to generate hardware interrupt requests.
0 OR interrupts disabled (use polling).
1 Hardware interrupt requested when OR = 1.
Noise Error Interrupt Enable — This bit enables the noise flag (NF) to generate hardware interrupt requests.
0 NF interrupts disabled (use polling).
1 Hardware interrupt requested when NF = 1.
Framing Error Interrupt Enable — This bit enables the framing error flag (FE) to generate hardware interrupt
requests.
0 FE interrupts disabled (use polling).
1 Hardware interrupt requested when FE = 1.
Parity Error Interrupt Enable — This bit enables the parity error flag (PF) to generate hardware interrupt
requests.
0 PF interrupts disabled (use polling).
1 Hardware interrupt requested when PF = 1.
R7
T7
0
7
Table 11-7. SCIxC3 Register Field Descriptions (continued)
R6
T6
0
6
Figure 11-11. SCI Data Register (SCIxD)
MC9S08GB60A Data Sheet, Rev. 1.02
R5
T5
0
5
R4
T4
0
4
Description
R3
T3
3
0
R2
T2
2
0
Freescale Semiconductor
R1
T1
0
1
R0
T0
0
0

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