mc9s08gt32a Freescale Semiconductor, Inc, mc9s08gt32a Datasheet - Page 56

• Manufacturer Part Number: mc9s08gt32a
• Description: Hcs08 Microcontrollers 8-bit Microcontroller Family
• Manufacturer: Freescale Semiconductor, Inc

Chapter 4 Memory
56
Reset
PRDIV8
DIV[5:0]
DIVLD
Field
7
6
5
W
R
DIVLD
Divisor Loaded Status Flag — When set, this read-only status flag indicates that the FCDIV register has been
written since reset. Reset clears this bit and the first write to this register causes this bit to become set regardless
of the data written.
0 FCDIV has not been written since reset; erase and program operations disabled for flash.
1 FCDIV has been written since reset; erase and program operations enabled for flash.
Prescale (Divide) Flash Clock by 8
0 Clock input to the flash clock divider is the bus rate clock.
1 Clock input to the flash clock divider is the bus rate clock divided by 8.
Divisor for Flash Clock Divider — The flash clock divider divides the bus rate clock (or the bus rate clock
divided by 8 if PRDIV8 = 1) by the value in the 6-bit DIV5:DIV0 field plus one. The resulting frequency of the
internal flash clock must fall within the range of 200 kHz to 150 kHz for proper flash operations. Program/erase
timing pulses are one cycle of this internal flash clock, which corresponds to a range of 5 μs to 6.7 μs. The
automated programming logic uses an integer number of these pulses to complete an erase or program
operation. See
DIV5:DIV0 for selected bus frequencies.
0
7
200 kHz
150 kHz
20 MHz
10 MHz
8 MHz
4 MHz
2 MHz
1 MHz
f
Bus
= Unimplemented or Reserved
PRDIV8
if PRDIV8 = 1 — f
(Binary)
PRDIV8
Equation 4-1
if PRDIV8 = 0 — f
0
6
1
0
0
0
0
0
0
0
Figure 4-4. Flash Clock Divider Register (FCDIV)
Table 4-7. Flash Clock Divider Settings
Table 4-6. FCDIV Field Descriptions
MC9S08GB60A Data Sheet, Rev. 1.02
DIV5
and
DIV5:DIV0
(Decimal)
0
5
FCLK
Equation
12
49
39
19
9
4
0
0
FCLK
= f
= f
Bus
4-2.
DIV4
Bus
0
4
192.3 kHz
÷ (8 × ([DIV5:DIV0] + 1))
200 kHz
200 kHz
200 kHz
200 kHz
200 kHz
200 kHz
150 kHz
Table 4-7
f
FCLK
Description
÷ ([DIV5:DIV0] + 1)
shows the appropriate values for PRDIV8 and
DIV3
3
0
Program/Erase Timing Pulse
(5 μs Min, 6.7 μs Max)
DIV2
5.2 μs
6.7 μs
0
5 μs
5 μs
5 μs
5 μs
5 μs
5 μs
2
Freescale Semiconductor
DIV1
0
1
Eqn. 4-1
Eqn. 4-2
DIV0
0
0