lf4415 LOGIC Devices Inc., lf4415 Datasheet - Page 11

• Manufacturer Part Number: lf4415
• Description: Video Memory / Fifo
• Manufacturer: LOGIC Devices Inc.

Mode Control
Pins
W/R Pointer
Contol Pins
LOGIC Devices Incorporated
Detailed Signal Definitions
MODE - Memory Organization DEfinition
The 4-bit MODE setting defines the memory organization in terms of depth, width, and number of unique
FIFO channels. See figures on page 5/6/7.
RDWRB - External Address Read/ Write pointer Override Control
When RDWRB is LOW, the external address ADDR defines the WRITE pointer - latched by bringing
WSET0 LOW. When RDWRB is HIGH, the external address ADDR defines the READ pointer - latched by
bringing RSET LOW. See Figure 4 on page 5.
WCLR0 - Write Pointer Clear 0
A LOW on WCLR0 clears the write address pointer to zero. When WCLR0 is brought LOW, a rising edge
of WCLK0 will write the current value on D0 to address 0 in memory . When WCLR0 is HIGH, the write
pointer auto-increments sequentially (unless WSET0 is brought LOW). WCLR0 may be programmed to be
edge-triggered, clearing the write pointer for a single cycle following a falling WCLR0 edge, after which a
sequential increment resumes. When active-LOW triggered, a LOW on WCLR0 forces the write pointer to
zero until brought HIGH. WCLR0 is only effective if WEN0 is LOW. In dual-channel modes (MODE=x1xx),
WCLR0 affects only the Channel 0 write pointer.
WCLR1- Write Pointer Clear 1
A LOW on WCLR1 clears the write address pointer to zero. WCLR1 may be programmed to be edge-
triggered, clearing the write pointer for a single cycle following a falling WCLR1 edge, after which a
sequential increment resumes. When active-LOW triggered, a LOW on WCLR1 forces the write pointer to
zero until brought HIGH. In single-channel modes (MODE=x0xx), tie WCLR1 LOW - unless used as an
ADDR external address bit (See ADDR descr.).
WSET0 - Write Pointer Set 0
When WSET0 is brought LOW, a rising edge of WCLK0 writes the data on D0[11:0] to the address
specified by the RDWR address control. WSET0 may be programmed to be edge-triggered, in which
case it ‘sets’ or ‘jumps’ the write pointer for only one clock cycle following a falling edge on WSET0, after
which auto incrementing resumes. When active-LOW triggered, a LOW on WSET0 overrides the write
pointer until it is brought HIGH. For prolonged address overrides, programming WSET0 to be active LOW
triggered while holding WSET0 LOW provides a continuous write pointer override. WSET0 is effective
only when WEN0 is LOW and WCLR0 is HIGH.
WSET1 - Write Pointer Set 1
In single-channel mode, WSET1 should be tied LOW. In dual-channel mode, WSET1 controls the Channel
1 write pointer as WSET0 controls the Channel 0 write pointer. WSET1 may be programmed to be edge-
triggered, in which case it ‘sets’ or ‘jumps’ the write pointer for only one clock cycle following a falling
edge on WSET1, after which auto incrementing resumes. When active-LOW triggered, a LOW on WSET1
overrides the write pointer until it is brought HIGH. WSET1 is effective only when WEN1 is LOW and
WCLR1 is HIGH. In single-channel modes (MODE=x0xx), tie WSET LOW - unless used as an ADDR
external address bit (See ADDR descr.).
RSET - Read Address Pointer Set
When a RSET is brought LOW, a rising edge of RCLK reads the address specified by the external address
port (assuming WCLR1/ADSEL is HIGH). RSET may be programmed to be edge-triggered, in which
case it ‘sets’ the read pointer for only one clock cycle following a falling edge on RSET, after which auto
incrementing resumes. When active-LOW triggered, a LOW on RSET overrides the read pointer until
it is brought HIGH. For prolonged address overrides, programming RSET to be active LOW triggered
while holding RSET LOW provides a continuous read pointer override. RSET is effective only when RENx
is LOW during the previous cycle and RCLR is HIGH. RSET cannot be brought LOW while WSETx
or are LOW.
www.logicdevices.com
11
PRELIMINARY
High Performance Memory Product
Video Memory / FIFO
January 23, 2008 LDS-44xx-A
FRAME
MEMORY
LF4460
LF4430
LF4415