lf4415 LOGIC Devices Inc., lf4415 Datasheet - Page 8

• Manufacturer Part Number: lf4415
• Description: Video Memory / Fifo
• Manufacturer: LOGIC Devices Inc.

Programming
the LF44xx
Serial MPU
Interface
LOGIC Devices Incorporated
Device Configuration
Most LF44xx applications will not require the internal configuration registers to be modified from their default
settings. If access to a special-purpose mode/feature is required, an I
written, the updated 8bit configuration modify the working circuitry only after writing an update command to
Register 03F. (See note at the end of this section).
The standard two-wire interface is composed of an SCL clock pin and a bi-directional SDA data pin. When
inactive, SDA and SCL are forced HIGH by external pull up resistors.
Data transmission is achieved over the SDA pin and must remain constant during the logical HIGH portion
of the SCL clock pulse. The level of SDA, while SCL is HIGH, is interpreted as the appropriate bit value as
will be shown later. Changing the data on SDA must only occur when SCL is low, because any changes
to SDA while SCL is HIGH is interpreted as a start or stop request, which are shown in Figure 7 with an
example data transfer in Figure 8.
The first operation to begin programming the LF4430 through the serial interface, is to send a start signal.
When the interface is inactive, a HIGH to LOW transition must be sent on SDA while SCL is HIGH, notifying
all connected devices (slaves) to expect a data transmission. When transferring data, the MSB of the eight
bit sequence is the first bit to be transmitted to or from the master or slave. The first byte of data to be
transmitted on SDA must consist of the 7-bit base address of the slave, along with an 8th READ/WRITE bit
as the LSB, which describes the direction of the data transmission. The slave whose 7-bit CHIP_ADDR6-0,
matches the 7-bit base address sent on SDA, will send an acknowledgement back to the master by bringing
SDA LOW on the 9th SCL pulse.
During a write operation, if the slave does not send an acknowledgment back to the master device, SDA is
left high which forces the master to generate a stop signal. In contrast, during a read operation, if there is no
acknowledgement back from the master device, the LF44xx interprets this as if it were the end of the data
transmission, and leaves SDA high, allowing the master to generate its stop signal.
SDA
SCL
Figure 7 - I
Figure 8 - Initiation and Data Transfer (to consecutive registers) on I
www.logicdevices.com
START
SDA
SCL
ADDRESS
2
C Start and Stop Signals
1-7
R / W
8
Start Signal
ACK
9
8
DATA
1-8
PRELIMINARY
SDA
ACK
SCL
9
High Performance Memory Product
2
C serial interface is provided. Once
Video Memory / FIFO
DATA
1-8
Stop Signal
2
C Bus
January 23, 2008 LDS-44xx-A
FRAME
MEMORY
ACK
9
LF4460
LF4430
LF4415
STOP