lf4415 LOGIC Devices Inc., lf4415 Datasheet - Page 14

• Manufacturer Part Number: lf4415
• Description: Video Memory / Fifo
• Manufacturer: LOGIC Devices Inc.

Flag Outputs
JTAG
LOGIC Devices Incorporated
PF0 / PF1 goes HIGH (active) when the write pointer is more than
(MAX_depth - (FullThresh)) locations ahead of the read pointer. FulThresh0 and FulThres1 are user
programmable threshold values for channel 0 and 1 respectively and are written into Registers 13-15
and 16-18. See Excel File in the ‘Video Memory Application Notes’ area on www.logicdevices.com
for specific threshold values. PF0 is updated on the rising edge of WCLK0. In Dual-Channel mode,
PF1 is updated on the rising edge of WCLK1 and is tristated in dual channel mode. In single-channel
modes, PF1 must be tied off unless used as an external address it (refer to ADDR discussion).
PE0 / PE1 - Programmable Almost Empty Flag 0 & 1
PE0 / PE1 goes HIGH (active) when the write pointer is less than or equal to
(MAX_depth - (EmpThreshX )) locations ahead of the read pointer. EmpThresh0 and EmpThresh1 are
user programmable threshold values for channel 0 and 1 respectively and are written into Registers 0D-0F
and 10-12. See Excel File in the ‘Video Memory Application Notes’ area on www.logicdevices.com for
specific threshold values. PE0 and PE1 are updated on the rising edge of RCLK. In single-channel
modes, PE1 must be tied off unless used as an external address it (refer to ADDR discussion)
COLLIDE0 - Memory Read/Write Pointer Collision Flag 0
COLLIDE0 is activated (HIGH) when the write/read address pointers collide/coincide. By monitoring the
partial full/empty flags, the user can determine the direction of approach, i.e., read pointer catching up
with write (FIFO empty) or write pointer catching up with read (FIFO full). COLLIDE0 is updated on
the rising edge of RCLK.
COLLIDE1 - Memory Read/Write Pointer Collision Flag 1
In dual-channel mode, COLLIDE1 is activated (HIGH) when the write/read address pointers collide/
coincide. By monitoring the partial full/empty flags, the user can ascertain the direction of
approach, i.e., read pointer catching up with write (FIFO empty) or write pointer catching up with
read (FIFO full). COLLIDE1 is updated on the rising edge of RCLK. In single-channel modes,
COLLIDE1 must be tied off unless used as an external address it (refer to ADDR discussion).
TDI - JTAG input data
TDI is the input data pin when using JTAG.
TDO - JTAG output data
TDO is the output data pin when using JTAG.
TMS - JTAG Tap controller input
TMS controls the state of the tap controller.
TCK - JTAG clock
TCK is the used supplied clock of JTAG. It controls the flow of data and latches input data on the
rising edge.
PF0 / PF1 - Programmable Almost Full Flag 0 & 1
www.logicdevices.com
14
PRELIMINARY
High Performance Memory Product
Video Memory / FIFO
MEMORY
FRAME
January 23, 2008 LDS-44xx-A
LF4460
LF4430
LF4415