lf4415 LOGIC Devices Inc., lf4415 Datasheet - Page 29

• Manufacturer Part Number: lf4415
• Description: Video Memory / Fifo
• Manufacturer: LOGIC Devices Inc.

LOGIC Devices Incorporated
1. Maximum Ratings indicate stress specifications only. Functional operation of these products
at values beyond those indicated in the Operating Conditions table is not implied. Exposure to
maximum rating conditions for extended periods may affect reliability.
2. The products described by this specification include internal circuitry designed to protect the
chip from damaging substrate injection currents and accumulations of static charge. Neverthe-
less, conventional precautions should be observed during storage, handling, and use of these
circuits in order to avoid exposure to excessive electrical stress values.
3. This device provides hard clamping of transient undershoot. Input levels below ground will be
clamped beginning at TDBV.
4. Actual test conditions may vary from those designated but operation is guaranteed as speci-
fied.
5. I/O Ring supply power for a given application can be approximated by:
where
6. Tested with 30 output pins driving 10pF loads, while toggling at an average of 30% of the
150MHz clock rate at 1.96V. This number will change depending on VCCo level. The 10pF load
is estimate of trace and downstream pin capacitance.
7. These parameters are guaranteed but not 100% tested.
8. AC specifications are tested with input transition times less than 3 ns, output reference levels
of 1.5 V (except t dis test), and input levels of nominally 0 to 3.0V(when using 3.3V IO voltage).
Output loading may be a resistive divider which provides for specified IOH and IOL at an output
voltage of VOH min and VOL max respectively. Alternatively, a diode bridge with upper and lower
current sources of IOH and IOL respectively, and a balancing voltage of 1.5 V may be used (when
using 3.3V IO voltage). Parasitic capacitance is 30 pF minimum, and may be distributed.
9. Each parameter is shown as a minimum or maximum value. Input requirements are specified
from the point of view of the external system driving the chip. Setup time, for example, is specified
as a minimum since the external system must supply at least that much time to meet the worst-
case requirements of all parts. Responses from the internal circuitry are specified from the point
of view of the device. Output delay, for example, is specified as a maximum since worst-case
operation of any device always provides data within that time.
10. For the t ena test, the transition is measured to the 50% crossing point with datasheet loads.
For the t dis test, the transition is measured to the ±200mV level from the measured steady-state
output voltage with ±datasheet loads. The balancing voltage, V th , is set at VCCo min for Z-to-0
and 0-to-Z tests, and set at 0 V for Z-to-1 and 1-to-Z tests.
11. These parameters are only tested at the high temperature extreme, which is the worst case
for leakage current.
Notes
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
www.logicdevices.com
NCV F
2
2
29
PRELIMINARY
High Performance Memory Product
Video Memory / FIFO
MEMORY
FRAME
January 23, 2008 LDS-44xx-A
LF4460
LF4430
LF4415