lf4415 LOGIC Devices Inc., lf4415 Datasheet - Page 12

• Manufacturer Part Number: lf4415
• Description: Video Memory / Fifo
• Manufacturer: LOGIC Devices Inc.

LOGIC Devices Incorporated
Detailed Signal Definitions
EDGE - Edge/Level Sensitivity Triggering for Address ‘SET’ Control
The EDGE pin controls whether WSETx, WSETx, RSETx are level or negative-edge triggered. When
level-sensitive, the appropriate pointer is overridden as long as the WSETx/RSETx pin is LOW. When
falling edge sensitive, a falling edge on one of the WSETx/RSETx pins triggers a single cycle of address
override (to the value on the 24bit ADDR external address). Individual sensitivity control over any SET
and CLR pin is possible by modifying Register A which overrides the settings preset by EDGE. The table
below outlines the EDGE pin settings.
RCLR - Read Address Pointer Clear
RCLR clears the read pointer. When RCLR is brought LOW, a rising edge of RCLK will read from address
0 in memory . When RCLR is HIGH, the read pointer auto-increments sequentially unless RSET is
brought LOW. RCLR may be programmed to be edge-triggered, in which case it clears the read pointer
for only one clock cycle following a falling edge on RCLR, after which auto incrementing resumes. When
active-LOW triggered, a LOW on RCLR forces the read pointer to zero until it is brought HIGH. RCLR is
only effective if REN0 is LOW. In dual-channel mode, RCLR clears both Channel 0 & 1 read pointers. The
read enables RENx must be LOW on the previous cycle to clear their respecitve read pointers.
WEN0 - Write Enable 0
WEN0 enables/disables memory write accesses and write pointer auto-incrementing. D0 data is written
into memory and the write address pointer is incremented on the rising edge of WCLK0 when WEN0
is LOW.
WEN1 - Write Enable 1
In dual-channel mode, WEN1 enables/disables Channel-1 memory write accesses and write pointer auto-
incrementing. D1 data is written into memory and the write address pointer is incremented on the rising
edge of WCLK1 when WEN1 is LOW. In single-channel mode, WEN1 should be tied LOW - unless used
as an ADDR external address bit (See ADDR descr.).
WIEN0 - Memory Write Enable 0 (Write Masking)
WIEN0 is used to disable writing into memory independent of the write pointer increment. A LOW on
WIEN0 enables writing, while a HIGH on WIEN0 disables writing. The write address pointer is incremented
by WEN0 regardless of WIEN0. WIEN0 can be used to mask data from being written to memory while the
write pointer freely increments. Unless writes to memory are to be masked, simply tie WIEN0 LOW and
let WEN0 handle memory/pointer enabling.
WIEN1 - Memory Write Enable 1 (Write Masking)
In dual-channel mode, WIEN1 is used to disable writing into channel-1 memory. A LOW on WIEN1 enables
writing, while a HIGH on WIEN1 disables writing. The write address pointer is incremented by WEN1
regardless of WIEN1. WIEN1 can be used to mask data from being written to memory while the write
pointer remains free running (incrementing). Unless writes to memory are to be masked, simply tie WIEN1
LOW and let WEN1 handle memory/pointer enabling. In single-channel mode, tie WIEN1 LOW - unless
used as an ADDR external address bit (See ADDR descr.).
Figure 9 - ‘Set’ Trigger Control
EDGE
www.logicdevices.com
0
1
WSET0
Edge
Level
WSET1
Edge
Level
RSET
Level
Edge
12
PRELIMINARY
High Performance Memory Product
Video Memory / FIFO
MEMORY
FRAME
January 23, 2008 LDS-44xx-A
LF4460
LF4430
LF4415